1 Random Number Generator Dmitriy Solmonov W1-1 David Levitt W1-2 Jesse Guss W1-3 Sirisha Pillalamarri W1-4 Matt Russo W1-5 Design Manager – Thiago Hersan March 29, 2006 Functional Blocks & Simulation Project Objective: Create a Cryptologically Secure Pseudo-Random Number Generator that will revolutionize chaos

2 Status Former C implementation Architecture Behavioral Design and Simulation Gate-Level Design and Simulation Preliminary Floorplan Schematic Design and Simulation Currently  Layout SRAM Adder Registers Counters Data Path Components Control Logic  Global Layout (~60% complete) Awaiting Global LVS, post-layout simulation

3 Design Decisions Clock Spine –Ensure rising edge of the clock is same for each register Equal sized, equal spaced buffer at the clock pin

4 FSM

5 Global Layout: Upper Part

6 Global Layout: Adder & Register Feedback

7 Floorplan

8 Global with Projected Interconnect

9 Global Layout

10 32 Bit Fast Adder Update

11 Pin Orderings Output pins are not in order Does not actually matter –Random Number

12 Timing Diagram for Adder

13 ComponentTransistor Count AreaProp DelayPower 500 MHz Adders (4)5856 (1464 each) 25,200 um2 (6300um2 ea.) 1.45 ns600 uW SRAM17736 (M=10458 R=7278) 8000 um2735psW: 510 uW R: 190 uW Registers (10)6400 (640 each) 38,400um2 (3840um2 ea.) 250 ps3.3 mW Total ,900um2500 MHz~6.5 mW Putting it All Together

14 Thanks for Listening. Questions?