High Speed Digital Systems Lab Spring/Winter 2010 Midterm presentation Instructor: Rolf Hilgendorf Students: Elad Mor, Ilya Zavolsky Integration of an A/D Converter Into The Sub-Nyquist Xampling System

2 Topics Project overview. Project overview. Progress made since characterization presentation. Progress made since characterization presentation. Initial receiver block diagram. Initial receiver block diagram. State machine. State machine. Initial simulation test result. Initial simulation test result. New given Guidelines and receiver technology plan overview. New given Guidelines and receiver technology plan overview. Time table Time table Integration of an A/D into Xampling System

Project Overview 3 Integration of an A/D into Xampling System Our goal is to integrate a sub-system that would convert the incoming analog samples to digital signals. Then they will be processed and reconstructed in the sub-Nyquist Sampling system. Our goal is to integrate a sub-system that would convert the incoming analog samples to digital signals. Then they will be processed and reconstructed in the sub-Nyquist Sampling system. For this purpose we shall use the TI ADS6423 Evaluation module. For this purpose we shall use the TI ADS6423 Evaluation module.

Progress made since characterization presentation Understanding the system requirements. Understanding the system requirements. Acquisition of working tools (Quartus, ModelSim, ProcWizard). Acquisition of working tools (Quartus, ModelSim, ProcWizard). Design of the initial receiver/transmitter. Design of the initial receiver/transmitter. Design of Control Logic for the circuit. Design of Control Logic for the circuit. Running Circuit Simulation on ModelSim for validation purposes. Running Circuit Simulation on ModelSim for validation purposes. Analysis of Simulation Results. Analysis of Simulation Results. Research of ideal settings for Receiver Implementation. Research of ideal settings for Receiver Implementation. 4 Integration of an A/D into Xampling System

Initial transmitter-receiver block diagram 5 Integration of an A/D into Xampling System

Controller State Diagram 6 Integration of an A/D into Xampling System

Controller State Machine Diagram 7 Integration of an A/D into Xampling System

Initial simulation test results 8 Integration of an A/D into Xampling System

The Altera Stratix III Differential signals Receiver 9 Integration of an A/D into Xampling System The Stratix III device has dedicated circuitry to receive high-speed differential signals. The Stratix III device has dedicated circuitry to receive high-speed differential signals. The receiver has a differential buffer, PLL, DPA block, synchronization FIFO buffer, data realignment block, and a deserializer. The receiver has a differential buffer, PLL, DPA block, synchronization FIFO buffer, data realignment block, and a deserializer.

New given Guidelines and our plan for the receiver technology According to Gidel we shall not be able to use Source Synchronous Receiver – almost certain that it won’t work properly. According to Gidel we shall not be able to use Source Synchronous Receiver – almost certain that it won’t work properly. We now aim to use a DPA (Dynamic Phase Alignment) for the alignment of the data bits. We now aim to use a DPA (Dynamic Phase Alignment) for the alignment of the data bits. The BitSlip Mechanism will be used for word Synchronization. The BitSlip Mechanism will be used for word Synchronization. The ADS6423 A/D card offers transmission test patterns that we intend to use. The ADS6423 A/D card offers transmission test patterns that we intend to use. Single PSDB connection can mix LVDS and Non-LVDS pins. Single PSDB connection can mix LVDS and Non-LVDS pins. 10 Integration of an A/D into Xampling System

DPA Circuitry 11 Integration of an A/D into Xampling System

Bit Slip Mechanism 12 Integration of an A/D into Xampling System Skew in the transmitted data along with skew added by the link causes channel-to-channel skew on the received serial data streams. If DPA is enabled, the received data is captured with different clock phases on each channel. This may cause the received data to be misaligned from channel to channel. To compensate for this channel-to-channel skew and establish the correct received word boundary at each channel, each receiver channel has a dedicated data realignment circuit that realigns the data by inserting bit latencies into the serial stream.

13 Time table (Semester A) Task \ Week July 1 July 2 July 3 July 4 August 1 August 2 August 3 ProcWizard Channel Lift Design an adapter card Design of the A/D Controller Final Design of LVDS Receiver Integration of the system Form a debug strategy Integration of an A/D into Xampling System

14 Questions / Answers Thank you! Integration of an A/D into Xampling System