1. High Speed Digital Systems Lab Spring/Winter 2010 Part A final presentation Instructor: Rolf Hilgendorf Students: Elad Mor, Ilya Zavolsky Integration of an A/D Converter Into The Sub-Nyquist Xampling System

2. Progress made since midterm presentation Design of transmission test environment. Design of transmission test environment. Performing speed tests to try and find the highest frequency for valid transmission (Loop-Back). Performing speed tests to try and find the highest frequency for valid transmission (Loop-Back). Design of A/D & NI adapters. Design of A/D & NI adapters. Examination of assembled adapters (Voltage levels, Pin matching). Examination of assembled adapters (Voltage levels, Pin matching). Design of advanced VHDL testing environment for the A/D adapter. Design of advanced VHDL testing environment for the A/D adapter. Execution of a single channel and a full width transmission (A/D->Adapter->StratixIII). Execution of a single channel and a full width transmission (A/D->Adapter->StratixIII). 2 Integration of an A/D into Xampling System

3. Transmission test environment Exploring and learning how to use the STRATIX I/O DPA and BITSLIP circuitry. Exploring and learning how to use the STRATIX I/O DPA and BITSLIP circuitry. Planning and implementing a control scheme to operate the design with the added features. Planning and implementing a control scheme to operate the design with the added features. Clock was looped-back as well. Clock was looped-back as well. Tackling different timing problems while elevating the transmission frequency. Tackling different timing problems while elevating the transmission frequency. 3 Integration of an A/D into Xampling System

4. Description of the data path of transmission test module The input data to the transmitter is selected by a state machine, which selects the source according to the stage of the system. At first, the alternating pattern “1010..” is used for Data Phase Alignment procedure. The second pattern is “111000” which is used for the BITSLIP operation. The third is used to determine the channel’s transmission delay. The fourth is the data generated by the counter. The input data to the transmitter is selected by a state machine, which selects the source according to the stage of the system. At first, the alternating pattern “1010..” is used for Data Phase Alignment procedure. The second pattern is “111000” which is used for the BITSLIP operation. The third is used to determine the channel’s transmission delay. The fourth is the data generated by the counter. In the receiving side, the data is inserted into the STRATIX ALTLVDS megafunction. In the receiving side, the data is inserted into the STRATIX ALTLVDS megafunction. From there it is moved into an internal FIFO for clock domain synchronization purposes. From there it is moved into an internal FIFO for clock domain synchronization purposes. Then it is driven out of the circuit to the Gidel PROCSTAR External FIFO to be read and verifyed after the transmission. Then it is driven out of the circuit to the Gidel PROCSTAR External FIFO to be read and verifyed after the transmission. 4 Integration of an A/D into Xampling System

5. Transmission test module Block diagram 5 Integration of an A/D into Xampling System

6. LVDS STRATIX3 tests results We have managed to reach 130MHz frequency transmitting a 6 bit word=780 Mbps. We have managed to reach 130MHz frequency transmitting a 6 bit word=780 Mbps. Trying to lift up the frequency we received high BER, expressing in false data in the FIFO. Trying to lift up the frequency we received high BER, expressing in false data in the FIFO. 6 Integration of an A/D into Xampling System

7. Design of A/D & NI adapters The goal of the ADA & NI adapters is to implement the communication hardware between the following devices: The goal of the ADA & NI adapters is to implement the communication hardware between the following devices: A/D convertor (ADS6423) A/D convertor (ADS6423) National Instruments 6585 FlexRIO module National Instruments 6585 FlexRIO module Gidel Card PROCSTAR III board Gidel Card PROCSTAR III board We started to work on a card which would provide all connectivity between the above on single card. We started to work on a card which would provide all connectivity between the above on single card. The idea was later abandoned for complexity and poor stability of the design. The idea was later abandoned for complexity and poor stability of the design. At this stage, we have decided to split the card into two cards – each for every device. In this way, we achieved improved flexibility, reduced complexity and better signal integrity. At this stage, we have decided to split the card into two cards – each for every device. In this way, we achieved improved flexibility, reduced complexity and better signal integrity. 7 Integration of an A/D into Xampling System

8. Adapters design procedure Orcad design to define the connectivity between the modules. Orcad design to define the connectivity between the modules. Sizing to match the system’s constraints; thickness to provide stability, width and length to match the GIDEL physical dimensions, Placement of the adapter’s components. Sizing to match the system’s constraints; thickness to provide stability, width and length to match the GIDEL physical dimensions, Placement of the adapter’s components. External layout performed by Aharon and validated by group. External layout performed by Aharon and validated by group. PCB was manufactured and assembled. PCB was manufactured and assembled. 8 Integration of an A/D into Xampling System

9. Final A/D adapter design 9 Integration of an A/D into Xampling System Silkscreen Signal Layout

10. Final NI adapter design 10 Integration of an A/D into Xampling System Silkscreen Signal Layout

11. Execution of a single channel and a full width transmission After examining the assembled adapters (Voltage, connections), we could perform a full link test (A/D to Adapter to Gidel card). We have used a training pattern option of the A/D, to transmit a known pattern. First, we have sampled a single channel, and after succeeding we have performed a full width transmission. Expected pattern: "00111000"=0x38 Received pattern: "00011100 " =0x1C 11 Integration of an A/D into Xampling System BITSLIP REQUIRED!

12. Plans for Part B Upgrading the circuit capabilities to perform the BITSLIP operation (like done before in test env’). Upgrading the circuit capabilities to perform the BITSLIP operation (like done before in test env’). Performing further examination of the link using different training patterns and specially designated data. Performing further examination of the link using different training patterns and specially designated data. Through transmitting full-width ascending pattern we will determine if two input channels are synchronous sampled. Through transmitting full-width ascending pattern we will determine if two input channels are synchronous sampled. Testing the A/D operation on a set of foretold signals, to determine permitted input voltage swing and over-all A/D validation. Testing the A/D operation on a set of foretold signals, to determine permitted input voltage swing and over-all A/D validation. Designing the Final Receiver module. Designing the Final Receiver module. Cooperate with the architecture team to form a final transmission interface. Cooperate with the architecture team to form a final transmission interface. 12 Integration of an A/D into Xampling System

13. (Channels sync diagram) 13 Integration of an A/D into Xampling System

14. 14 Questions / Answers Thank you! Integration of an A/D into Xampling Syste