1. By: Oleg Schtofenmaher Maxim Fudim Supervisor: Walter Isaschar Characterization presentation for project Winter 2007 ( Part A)

2. General overview  Software solutions for real-time are too slow  Power dissipation limits work frequencies  Greater computing power needed  H/W accelerators can improve s/w processes  Multi-core, multi-threaded systems are the future

3. Problem  How to manage multiple parallel units?  How to achieve full and effective utilization of resources?

4. Solution Load Balancing Switch  Converting shared resources to “personal” work space.  Smart management of system  Monitoring of each unit’s load

5. Our system’s workspace  High data rate input  Vectors of various length  Variable number of accelerators  Undetermined single unit run time  Variable number of FPGAs  Need to organize input & output vectors

6. System Block diagram Input vectors Load Balancing Switch (LBS) Output reports NIOS II S/W or H/W generator S/W or H/W consumer DDR2 Bank A Data and Control Stratix II FPGAPROCStar II DDR2 Bank B

7. LBS Block diagram Main Controller unit DDR2 Input FIFO Output FIFO FPGA Output Controller unit Cluster Arbiter Cluster Buffer/s Cluster Arbiter Cluster Buffer/s Cluster Arbiter Cluster Buffer/s To NIOS II Clusters NIOS II outputs Control PCI NIOS II

8. S/W and H/W Tools Hardware:  GIDEL’s PROCStar II Board w. single Altera Stratix II 60 FPGA (four Stratix II 180 FPGAs in future). Software:  PROCWizard 8.1  Quartus 7.1  HDL Designer 2005  NIOS II IDE  Visual Studio 2005  Gidel API

9. Tasks  Study PROCStar Board – Done  Study Altera’s Stratix II FPGA – Done  Study Quartus and HDL designer– Done  Study GIDEL API – Done  Learn to use Signal Tap tool – Done  Study Altera’s NIOS II – Done  Define interface with software group – Done  Develop signal generator for testing – Done

10. Tasks (cont.)  Define interface with accelerator group  Build direct connection between s/w and NIOS II  Expand design for several NIOS’s  Define algorithm for smart switch and load balancing  Implementation and debugging of the switch  Integration of entire system