1. General Purpose FIFO on Virtex-6 FPGA ML605 board midterm presentation
Students:
Oleg Korenev
Eugene Reznik
Supervisor:
Rolf Hilgendorf
Semester: spring 2012

2. Content Project overview Goals Specifications HW Block Diagram
MEMORY on ml605
AXI4
Design Block Diagram
Accomplished so far
Workflow
Timeline

3. Project Overview
Design and implementation of General Purpose FIFO IP core which allows usage of external memory (DDR3) as FIFO storage on Xilinx FPGA device
Design and implement generic IP core of FIFO
Design and implement GUI generator of IP core on PC
Create sample design with implemented IP core

4. Our goals Gain experience in hardware development (VHDL environment)
Explore and expertise FPGA work environment
Create design with configurable
word size
FIFO depth
Achieve best performance
Minimize usage of FPGA resources
Make our world a better place

5. Specifications Hardware Software
Xilinx Virtex-6 ML605 FPGA Evaluation Kit
DDR III memory
Ethernet interface
PCIe interface
PC with Ethernet interface
Software
ISE Design Suite Logic Edition Version 13.2
Modelsim

6. PC HW Block Diagram ML605 BOARD VIRTEX6 DDR3 MEMORY USER DESIGN
FIFO CORE
ETHERNET/PCIe PC

7. MEMORY on ml605 DDR3 memory Capacity: 512MB
Max theoretical bandwidth: 800MT/s*64bit = 6.4GB/sec
Xilinx provides us with DDR3 controller which has AXI Memory Mapped interface
AXI bus data width up to 1024 bit
256 bit for max memory performance, assuming bus works with 200Mhz

8. 4AXI
Xilinx provides us with AXI4 Memory Mapped bus, which is a standard bus used in modern ARM SoC.
Features
Separate Address/Control and Data Phases
burst-based transactions with only start address issued
separate read and write data channels

9. AXI4 BUS (INTERCONNECT)
DESIGN Block Diagram
DDR3
HOST STORAGE
LOGIC STORAGE
USER STORAGE
MEMORY CONTROLLER
AXI4 BUS (INTERCONNECT)
ARBITER / CONTROLLER
FIFO TO MEMORY
F I F O
MEMORY TO FIFO
F I F O
FIFO TO MEMORY
F I F O
MEMORY TO FIFO
F I F O
LOGIC
Ethernet Interface
User Interface
ETHERNET
HOST

10. DESIGN Block Diagram DDR3 ARBITER / CONTROLLER LOGIC EMULATOR
HOST STORAGE
LOGIC STORAGE
USER STORAGE
MEMORY CONTROLLER
AXI4 BUS
ARBITER / CONTROLLER
FIFO TO MEMORY
F I F O
MEMORY TO FIFO
F I F O
FIFO TO MEMORY
F I F O
MEMORY TO FIFO
F I F O
LOGIC
EMULATOR
User Interface
User Interface

11. Accomplished so far External interface Defined basic FIFO interface
Defined word size limitation as 32 up to 1024 bit
Studied features and integrated AXI4 memory mapped bus
Connected DDR3 to AXI bus
Internal architecture
Implemented memory arbiter with basic functionality, connected to AXI bus as master
Implemented internal FIFO-To-Memory controller
Implemented internal Memory-To-FIFO controller
Implemented basic emulator of user logic for testing

12. Problems Placement in FPGA
We did not succeeded to place synthesized memory controller on chip.
Design
In which policy should memory arbiter work
Ethernet or PCIe?

13. Workflow Add AXI Interconnect for enabling User Logic to use memory
Improve AXI arbiter for best performance
Studying usage of Ethernet for communication with PC
Integrating Ethernet controller with AXI stream interface into design
Verification of design in hardware
Implementing GUI for generating FIFO IP core
Testing
Implementing sample design

14. Timeline Task 1 week 2 weeks 3 weeks Duration
2/9
26/8
19/8
12/8
5/8
29/7
exams
24/6
17/6
Duration
Task
1 week
Integrate AXI interconnect into design
2 weeks
Complete AXI arbiter functionality
Studying and integrating Ethernet controller into design
3 weeks
Verification design in hardware including communication with PC
Part A Presentation