1. Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke Instructor Mony Orbach Duration Single Semester

2.  Project overview.  Card Spec’s.  Hardware: ◦ Block Diagram of the Card. ◦ Circuit diagram of the card.  Interface between the Analog card and the DE2.  Software: DE2 functions

3.  What is in the lab today? closed lab experiment consisting of only an 12 bit A/D and a sample and hold.  What are the new features in our project?  8 bit A/D converter (less sensitive to digital noise)  D/A converter.  DE2 board Our card will allow the students to process the digital signal and observe its effects on the reconstructed signal.

4.  Design and produce a Prototype card that has on it: 1. a sampler (plus an A/D) 2.a reconstructing unit (D/A).  External digital signal processing using the DE2 card.  Protect the card from users accidentally damaging it.

5. Students create on breadboard input circuit consisting of -> Anti-aliasing filter. -> Amplifier. A/D – D/A Card Students create on breadboard input circuit consisting of -> Smoothing filter. -> Power Amplifier. Design of a board for the new laboratory experiment in analog to digital conversion (ADC). DE2 Board

6.  General Function of the card: ◦ Samples & converts digital signal. ◦ Processed. ◦ Converted into analog signal.  Clock: ◦ External clock.  Input and output format: ◦ Unipolar format or ◦ Bipolar format.  Other options: ◦ Convert an signal that isn’t sampled. ◦ Not using the DE2 processing unit.  Protection: ◦ Voltage:  Clock  Analog signal ◦ Short circuit:  Analog output

7.  Supply voltages  +20V  -20V  Power consumption  Typically: ~3W  Max: ~4.2W  User interface Switches:  Input \ output is in Unipolar format or bipolar format.  input is sampled or not.  Clock frequency  Up to 50KHz.

8.  Inputs & outputs  Clock:  5 volt square wave.  Duty cycle (min. clock high 1uSec)  Analog input:  Bipolar: +/- 10 volt signal.  Unipolar: 0 to 10 volt signal.  Analog output:  Bipolar: +/- 10 volt signal.  Unipolar: 0 to 10 volt signal.

9.  Data transfer rate:  Data is transfered at the clock frequency (up to 50KHz)  data is ready at rising edge of the clock.  Test circuitry – test points: 1.At entrance to A/D. 2.Output of D/A.

10. -10 volt reference voltage for ADC 5 volt voltage regulator+15 volt voltage regulator -15 volt voltage regulator

14.  problem: ◦ ADC needed the clock to be high during the entire conversion time  Solution: ◦ we decided to add the following logic to the clock: clock’= clock OR not(nBusy) This way we can ensure that the duty cycle of clock’ will always ensure proper conversion by the ADC. Input clock nBusy Clock OR Not(nBusy) Not(nBusy)

15.  We chose the AD7574 as our ADC: ◦ Fit our price range. ◦ sample and hold. ◦ 8 bits. ◦ conversion time 16 uSec ◦ Three state outputs. ◦ ROM mode.  We chose the AD558 as our DAC: ◦ Settling time (1 uSec). ◦ 8 bits. ◦ Output voltage is 0 to 10 volts.

16.  AD781 is our S&H Amplifier: ◦ Internal hold capacitor.  LF411 is our operational Amplifier: ◦ Bandwidth of more than 1MHZ. ◦ Rail voltage is +/-15 volts.  74LS374 is our Buffer/Driver/Register: ◦ 8 bit digital. ◦ Three state outputs. ◦ Latches onto input at clock rising edge.

17.  Opcode (supplied directly to the DE2 by user): ◦ 8 bit – will determine the signal processing that is applied on the digital input.  Input: ◦ 8 bit digital input from the card of the sampled and converted input signal.  Output: ◦ 8 bit digital output of the processed signal to the card.  Data ready signal: ◦ Card Clock’ is input into the DE2 from the card and acts as a signal telling the DE2 when the input is valid.  Clock output: ◦ This feature allows the DE2 to control the DAC rate of conversion.

18.  Division of the input by two.  Saturation of the digital input signal.  applying the mathematical “log” function on the input signal.  Note: we will use the FPGA’s PLL in order to increase the speed of the processing of the signal.  If we have time we may also implement a digital filter function.

19. Analog card Register level DE2 inputs DE2 outputs סכימה גלובלית

20. קצת על הכרטיס LEDs switches Buttons FPGA Power Supply USB Blaster Clock (27 MHz) Expansion Header

21. דיאגרמת בלוקים

22. פונקציות שמומשו על הכרטיס

23. Div by 2Delay (pass the signal)saturateFirst-order hold

24. כניסות ויציאות של הכרטיס interface כניסות לכרטיס : Input data: 8 bits Control from the card : 2 bits Input control : 1 bit (unipolar / bipolar) : יציאות מהכרטיס Output data: 8 bits Control : 1bit (unipolar / bipolar) Clk : 1 bit (27 MHz)

25. ספציפיקציות Inputs and outputs specifications : 3.3 -V LVTTL Provided voltage : 5 V and 3.3 V הכרטיס נבדק ע " י התוכנות הבאות : Quartus 7.2 Modelsim 5.8b

26. ניצול משאבי הכרטיס (quartus results) Logic elements : 388/33216 (1 %) Registers : 128/33216 ( <1 %) Total pins : 48/475 ( 10% ) Total Memory bits : 4096/483840 (< 1% ) DSP 9x9 : 0/70 ( 0%) PLLs : 0/4 ( 0% )

27. כמו להרוג זבוב בעזרת טיל

28. שאלות ???????