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Sub-Nyquist Reconstruction Characterization Presentation Winter 2010/2011 By: Yousef Badran Supervisors: Asaf Elron Ina Rivkin Technion Israel Institute.

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Presentation on theme: "Sub-Nyquist Reconstruction Characterization Presentation Winter 2010/2011 By: Yousef Badran Supervisors: Asaf Elron Ina Rivkin Technion Israel Institute."— Presentation transcript:

1 Sub-Nyquist Reconstruction Characterization Presentation Winter 2010/2011 By: Yousef Badran Supervisors: Asaf Elron Ina Rivkin Technion Israel Institute of Technology

2 Project Overview Part of the Modulated Wideband Converter project cluster. – A system for sub-Nyquist sampling of multiband signals. Sub-module of the reconstruction block. To be implemented on a card consisting of 4 Altera Stratix III FPGAs, using a single FPGA.

3 Project Block Diagram

4 Input and Output Input: Sequences z[n] representing spectrum slices At most N sequences, one per slice Spectral support slices s Problem: Spectral support and carrier frequencies of bands are unknown. A single slice may contain more than one band (at most N/2). A single band might be divided between two slices.

5 Input and Output Output: A sequence of vectors, one per spectral slice. Each vector describes energy distribution in the slice; areas in the slice that hold energy. Requires high resolution vectors. OR A sequence of numbers, at most N/2 pairs of numbers per spectral slice. Each pair of numbers describes the beginning and end of energy in a slice.

6 Requirements and Resources Requirements – 18-bit fixed-point representation. – Fit VHDL implementation on Altera Stratix III FPGA EP3SE260. Resources —Reference floating-point MATLAB implementation. —Memory: 2.5 GB in 3 banks.

7 Resources (cont.)

8 Mathematical Tools Project Workflow Algorithm Resources & requirements Understand theory and reference implementation Propose alternative and equivalent calculation MATLAB Floating-point representation 18-bit fixed point representation Possible C implementation Find implementations of required mathematical operations in VHDL Implement missing tools in VHDL VHDL Design Creating a block diagram Designing the system in VHDL Design Simulation ModelSim Creat testbench for each VHDL design Simulations Synthesis Timing simulations using Altera Stratix III libraries

9 Gantt Chart

10 Thank you!


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