1 Project supervised by: Dr Michael Gandelsman Project performed by: Roman Paleria, Avi Yona 26/4/2004 Multi-channel Data Acquisition System Final_A Presentation.
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1 Project supervised by: Dr Michael Gandelsman Project performed by: Roman Paleria, Avi Yona 26/4/2004 Multi-channel Data Acquisition System Final_A Presentation
2 Presentation context Project description. General review Hardware Block diagram Data flow and storage algorithm Data flow and storage algorithm Software Computer communication Gui interface Gui interface
3 Project Description First the users asks to start the process We sample the data and store it at altera Analog sampling of Two synchronic signals. Analog sampling of Two synchronic signals. A-D process at accuracy steps of 2.5mv and at 500 kHz frequency. A-D process at accuracy steps of 2.5mv and at 500 kHz frequency. Data is loaded and filtered at ALTERA FPGA Data is loaded and filtered at ALTERA FPGA Integrator filter Integrator filter Than we Transfer the data to Computer. Gui interface: Controlling commands and viewing threw the computer
4 AtoD Data sampler I/O PCI bus lines Altera device calculates and stores the sampled data Main Block diagram Main Block diagram Data lines Control lines Analog inputs LabView Gui mux
5 Sub block - Data sampler Block diagram Mux 4 ⇨1 Channel B.Two general purpose inputs (For actions such as battery check..) Channel A, analog data inputs AD 1010 1101 000 Control lines Sampled data
6 Inputs Clk1,S – control which of 4 analog inputs(S1A:S4A) will be sampled. In our project we actually sample only 2 signals. So that S line is stable. Clk0 – Fall of this signal initializes the convert ion process. Outputs DB0:DB11 – Digital Data lines. EOC – Specifies when the Digital signal is ready. Sub block - Data sampler Functionality by signals
7 Memory Block ∑ Connector Card Clock generator Controlling logic ESP Sub Block - Control analyzer and memory
8 Computer to ALTERA commands 1. Commands Reset memory. Start sampling process Start data transfer process 2. Signals: 24 bits. 1Byte used to data transfer 1Byte used to data transfer Additional 2 bytes used for controlling and hand shacking protocol. Additional 2 bytes used for controlling and hand shacking protocol.
9 Sub block – Altera to Labview connections 8 bits PCI-DIO card controlled threw LabView Altera EPF10K100E
10 2 Triggers signals is used Trigger out – ALTERA gives a command to external analog signal generator to start. Trigger in – External signal generator inform that he start's generating the signal Sub block – Altera with analog devises - Trigger signals
11 sampling process – ALTERA controls Count =0 Trigger out Is trigger in Clock generate EOC = Rise R (Count) +=D0:12 Count<2048 Count++ Yes No Yes No Yes Done
12 Altera data analysis On each cycle the sampling data is added to the previous cycle data D1 D2 D1 D2..D1 D2 D1+D1 D2+D2 D1+D1 D2+D2. D1+D1 D2+D2 The sampling process is about to be evaluated 16 times, and only then to be transmitted to the computer
13 Data transfer to computer Count =0 Port A =R (Count)[0:7] Hand shaking – Done? Yes Port A =R (Count)[8:15] Hand shaking – Done? Yes Count ++ Count < 2048 Done No Yes
14 Software Lab View Chosen as interface program There would be a Gui featured: 1. Graph presenting the sampled data. 2. Process controlling buttons.