Team M1 Enigma Machine Milestone March, 2006 Design Manager: Prateek Goenka Adithya Attawar (M11) Shilpi Chakrabarti (M12) Mike Sokolsky (M14) Design Manager: Prateek Goenka

Status Finished: –Behavioral Verilog and C simulation –Structural Verilog –Logic optimization –Module-level spice delay and power simulations –Floorplan –Top-level schematic testing In Progress: –Functional block layout –Simulation of functional blocks To do: –Global Layout –Testing –Simulation STATUS

Layout done:Layout Needed: GatesROM Muxes and RegistersRAM DFF, TFF FlipflopsFSM Add_Mod263-bit and 5-bit serial input registers Wheel Counter CellsWheel Counter

Design Decisions Finalized the SRAM design Layout of Add_Mod26 Layout of 3-bit and 5-bit counter cells Updated layout of Wheel Counter Floorplan

Initial Floorplan

UPDATED FLOORPLAN

Schematic Delay: 68ps ExtractedRC Delay: 94ps Register

Schematic of Add_Mod26

LAYOUT OF ADD_MOD26

LOOKAHEAD MODULE LAYOUT

LOOKAHEAD 2 MODULE LAYOUT

SUBTRACTOR MODULE LAYOUT

3-bit Comparator

3-bit Counter Cell 3, 1-bit T Flips FlopsCount Logic

3-bit Counter

5-bit Counter Cell 5, 1-bit D/T Flips Flops Count Logic w/ Reset at 26

Wheel Counter Plan (Module layout and wire planning) 5-bit Counter Cell Data from counters Wheel Select Wheel Position 5-bit Counter Cell