1. 1 Lucas-Lehmer Primality Tester Presentation 9 March 29, 2006 Team: W-4 Nathan Stohs W4-1 Brian Johnson W4-2 Joe Hurley W4-3 Marques Johnson W4-4 Design Manager: Prateek Goenka Overall Objective: Modular Arithmetic unit with a creative use

2. 2 Status Finished –Project Chosen –C simulations –Behavioral Verilog –Structural Verilog –Floor Plan –Schematics –Pathmill Simulation of Top Level In Progress –Layout –Layout Simulations To Do –More Layout/Simulations

3. 3 Simulation Notes Top Level Schematic Simulation Full run of smallest “interesting” case (p=7) –5 hours on new machines –4 Gb disk space* *now that new machines have /scratch, we can use them. Tests are re-run nightly to preserve sanity.

4. 4 New “low-power” Registers Registers were overdue for an overhaul. Hacked together, very poor performance characteristics. Researched, decided to attempt a low power, or at least cleaner, design. Register layout not begun, best time to change things.

5. 5 Low Power Schematic

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7. 7 Measured Simulation Characteristics Clk-Q 175ps Rise 115ps Fall 100ps Power: 28.55uM @ 250 MHz Less than 1% savings. Top level sim results: –Old: 636.2 uM –New: 631.9 uM

8. 8 On the other hand… Initial extractedRC came out pretty badly Rise, Fall, Clk-Q all 3x longer. Obviously must handle with care Unless they clean up very very well, stick to a safter, practically-just-as-good conventional design.

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11. 11 More Power To You Other things helped far more –Switched largest multiplexers to n-pass* –Re-wrote several counters, turn off when not in use. –Removed unnecessary checking logic (only relates to cases larger than we can test). Power After Logic Changes: 438.7uM 30% less power. Embarrassingly better. Need to re-verify in detail.

12. 12 16-bit Subtraction

13. 13 Rise time, RC

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19. 19 General Purpose Shifter

20. 20 Modular Adder

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23. 23 Areas ModuleArea (μm 2 ) Count13,200* Partial Product38,000* Sub 163,240 Compare200* ModP5,600* Registers3,000* Mod_add5,200 FSM3,000* *Estimate

24. 24 Top Level Schematic

25. 25 Floorplan

26. 26 Partial Product Progress BlocksInstancesStatus Sub163DRC/LVS/sim Shift Left290% Layout Shift Right2100% Layout Muxes2DRC/LVS Logic (~200 transistors) 10% Layout FullAdder161DRC/LVS

27. 27 Overall Status BlocksInstancesStatus Mod Add1DRC/LVS/sim ModP (shifter)190% Layout Sub 161DRC/LVS/sim FSM/Count110% Layout Registers220% Layout Compare10% Layout

28. 28 What’s Next Layout Forever Continue Simulating Layout extractedRC power Optimize

29. 29 Problems Waveforms are correct, but not always pretty.

30. 30 Questions?