Xilinx Alliance Series Release 1.4 Features & Benefits 1

What’s New in 1.4 New Device Family Support Context Sensitive Help Highest Density with the XC4000XV High Speed ASIC replacement Spartan family including Select RAM Low Cost XC5200 & XC3x00 Context Sensitive Help Improved Reports and Feedback Constraints Cheat Sheet Easier License Setup Load & GO! Graphical License setup & modification 2

Higher Performance Through Simple Interfaces Fastest Runtime Best Results The Alliance Series 1.4 implementation software has elevated its ease-of-use quality. The tools are easier to use than ever. The addition of a new overall place and route level simplifies user selection between fast compile times and optimum design performance with the simple slide bar. Choose between fast compile times & optimum design performance 3

The Productivity Edge Easy to Track Design Change with Revision Control Industry’s Best Pin-Locking Capability Allows rapid prototyping & reduces manufacturing costs Powerful Iterative Design Flow Extensive Platform/OS Support Win95, WinNT 4.0, NEC PC98 Chinese, Korean & Japanese Windows Solaris 2.5, SunOS 4.1.3 & 4.1.4, HP-UX 10.2 Revision Control - This is something that Altera does not have. Emphasizing the tool’s ease-of-use and high performance attributes, the Alliance Series 1.3 added the design revision control feature to the Design Manager. The industry’s best pin-locking capability allows rapid prototyping and reduction in manufacturing costs. Powerful iterative design flow provides the ability easily make changes by not having to go back to the beginning of the design flow. You can make changes after synthesis or after mapping either in the design source or in the tool’s parameters to to increase performance. You can also heck timing before place and route to see if you have a chance to meet timing requirement. Xilinx’s OS support of EDA tools will coincide with its EDA partners’ platform support strategies. 7 4

The Performance Advantage Advanced HDL Methodology Support 25% Higher Performance with Distributed Processing > 95% Device Utilization Robust Timing Constraints Faster Design Times & High Performance with: LogiBLOX module generator LogiCORE core generator The Xilinx Alliance Series is designed to fit the ASIC design methodology. There is no need to learn a different design flow. Adoption of the industry standard netlists (VHDL, Verilog, EDIF, etc.) enables the Alliance Series system to provide prompt and up-to-date support of the new EDA design tools. Alliance Series software users can achieve design performance improvements up to 25% without incurring additional run time through the use of the Alliance Series Turns Engine tool. The Turns Engine tool provides users with numerous place and route iterations per design via networked UNIX workstations running multiple place and route passes. The Alliance Series Turns Engine tool, previously sold at an additional cost, is now included at no cost in the workstation version. Algorithm advancement in the place and route helps to achieve 95% to 100% device utilization while meeting your performance requirements. LogiBLOX as the next-generation module generator from Xilinx, replaces X-BLOX. It offers HDL functional simulation including VHDL or Verilog simulation models and reduce design entry time with an easy-to-use GUI. Xilinx LogiCORE products offer: 1. High-performance interface cores such as the PCI interface modules that require understanding and control of Xilinx’s FPGA technology and implementation software to achieve the desired performance and complexity. 2. LogiCORE DSP modules implemented using a unique algorithm, Distributed Arithmetic. This algorithm fits the look-up-table-based FPGA architecture. The result is maximum performance and device utilization, often more than 10 times better than generic HDL descriptions. 4 5

Runtime Improvements in 1.4 Using Default Effort Level 100% 80% 60% 1.4 Runtime Reduction 40% 20% 0% 5-13K Gates 28-62K Gates >85K Gates Design Size Place and route results measured against 1.3 Default is lower effort level, performance within 10% of previous defaults 6

1.4 Runtime Improvements New Defaults Speed Runtime Clock Speed L1 L=PAR Effort Level Runtime 7

Strengthening Our Partnership Synopsys for high density designers Powerful New FPGA Express Features Up to 100% faster compile times FPGA Express Ease-to-use speed vs area switch High Density Synopsys FPGA Compiler II Appnote Synopsys Synthesis and Simulation Design Guide 8

Strengthening Our Partnership Exemplar for high density designers Up to 15% Performance & 50% Utilization Improvements with Exemplar Full support for timing constraints optimization 9

Strengthening Our Partnership Synplicity JMA Announced 1/98 COOP AD in ISD Up to 30% performance improvements with Synplicity New mappers & new architecture support Timing constraints passing 10