1. Embedded systems, Lab 1: notes
programmable logic
Altera devices and the Altera tools
major tasks in the “silicon programming” process

2. "silicon compilation":
basic idea: restrict possible physical configurations; sacrifice area / performance for "regularity" of design; use regular physical structures to enable AUTOMATION of layout
All CAD tools will sacrifice some area/performance for automation and the ability to do "large" designs, just as software compilers sacrifice some efficiency for the ability to use a high-level language instead of assembly language; designer productivity will increase substantially, however
SW Programming:
Write Program (HLL)
Link to Libraries
Load/
Execute
Compile
Silicon Programming:
Com-pile/
Link to phys. libe
Write Program (HDL/Scm)
Program Device/
Execute
Fit
Simu-late

4. LE
(Logic Element)
LAB
(Logic Array Block)
RAM Block

5. Example: using a lookup table to describe a gate network:
f(A,B,C) = A'B'C + A'BC' + A'BC + ABC
Inputs: ABC out
000 0
001 1
010 1
011 1
100 0
101 0
110 0
111 1

6. Altera Project Flow (“Rapid Prototyping”):
1. (Hierarchical) DESIGN
design entry
schematic (mydesign.gdf)
vhdl, Verilog, …
IP cores
2.Compilation
translation, optimization, synthesis (“netlist”)
device fitting (placement and routing)
Floorplan editor
Report generation
3.”Execution”
Timing analysis
simulation (functional / timing)
device programming, hardware verification

7. DE-1 board: Cyclone® II 2C20 FPGA Technology: SRAM
General description:
General information on “programmable” devices:

10. Reconfigurable computing:
We can create arrays of programmable devices
Programmability will allow us to change the hardware capabilities "on the fly"--e.g., reprogram some devices while others are being used for processing; this allows us to "reconfigure" the hardware to adapt to specific processing needs, just as we can now rewrite software
example: Xilinx Virtex FPGA boards