1. Xilinx Alliance Series
Powerful High Density Solutions Integrated into Your EDA Environment
Xilinx offers two software product series:
The Alliance Series software provides designers with the flexibility to select the best EDA design environment for their application. Xilinx has built and nurtured close relationships with many of the industry's leading EDA tool vendors resulting in a wide range of design techniques including schematic capture HDL design, and module-based design. Combining the strengths of our partner’s tools with our own advanced implementation technology provides our customers with a powerful overall design solution.
Included in the Alliance Series are libraries and interfaces for several EDA environments along with comprehensive implementation tools. Contact your local EDA sales office to purchase the libraries marked with an asterisk. Aldec*, Cadence, LMG*, Mentor, OrCAD*, Synopsys, VeriBest*, VIEWlogic, Exemplar*, Synplicity*, Model Technology.
Extensive information about the Xilinx Alliance Series can be found on the WEBlink 1

2. Higher Densities & Performance Requires Powerful Software
Virtex
1M+ Systems Gates
System Solution
0.25/0.18µ
2.5/1.8 Volt
XC4000XV
Largest Device
500,000 sys. gates
0.25m
2.5 Volt
30% Faster than XL
Density/Performance
XC4000XL
Largest Device
180,000 sys. gates
0.35m
3.3 Volt
30% faster than EX
XC4000EX
Largest Device
XC4036EX
0.5m
5 Volt 30% faster than E
Xilinx’s FPGA densities and performance continue to make quantum leaps. This year we will have over 1 million system gates.
Today Xilinx is the industries leader in both high density FPGAs and high performance with the .25 micron XC4000XV family. The XC40250XV is the industries highest density FPGA at 500K system gates.
The introduction of Xilinx’s latest revolutionary family, Virtex, will not only provide you more gates and speed, this family will make designing FPGAs in an HDL environment even more powerful.
`High density and high performance PLDs requires the industries most powerful EDA tools. The Xilinx Alliance Series in conjunction with the industries leading front and back-end EDA tools will provide you the design environment to get your job done today and tomorrow.
1 Million Gates
in 1998
XC4000E
Largest Device
XC4025E
0.5m
5 Volt
Year
1995
1996
1997
1998
1999 2

3. The Alliance Series Advantage
Only Xilinx delivers these essential capabilities
Powerful timing-driven technology & graphical Constraints Editor
Highest performance with industries leading synthesis vendors
Dramatic productivity improvements with the Core Generator
Support for industries highest density FPGA XC40250XV 500K system gates
Guarantee your design performance with min & max timing
Only Xilinx delivers these essential capabilities:
Increase design performance with timing-driven place-and-route capabilities and the industry’s most robust timing language, SMARTspecs and an easy to use graphical Constraints Editor.
The FPGA/CPLD industries highest quality integration with premier EDA partners like Synopsys, Mentor, Cadence,Viewlogic, Synplicity, Exemplar, Veribest, OrCAD, Aldec and Model Technology. The leading EDA vendors recognize Xilinx as the industry leader and provide first and up-to-date Xilinx support giving the designer the ability to ‘try-out’ a device even before silicon is available.
The Xilinx CORE Generator is a software tool for generating and delivering parameterizable cores optimized for Xilinx FPGAs. Use the CORE Generator to design high-density Xilinx FPGA devices and achieve higher performance results plus a reduction in design time.
The Alliance Series 1.5 supports the complete line of Xilinx’s FPGAs and CPLDs: XC3x00A/L, XC5200, Spartan/XL, XC4000E/X, Virtex and XC9500 CPLDs. This includes the new XC4000XV device family.
Only Xilinx provides minimum and maximum delays in addition to voltage and temperature prorating factors. Guarantee your design performance with both minimum and maximum delays. See how fast your design can really go under favorable voltage and temperature conditions. This is something that Altera does not have. 3

4. Expanding the Leadership The latest Xilinx software delivers
Support for the industry’s 1st 1M gate FPGA Designs
The industries fastest timing-driven compile times
50% faster compile times
Max Design performance: AKAspeedtm technology
Up to 30% faster performance
Higher productivity with HDL Simulators Model Technology Eval in the Box
Web-enabled design tools
Alliance Series 1.5 expands the performance and timing-driven compile time leadership by delivering 50% faster compile times.
A key element is Xilinx’s new AKAspeed Technology, a suite of new algorithms and features designed to give users maximum design performance and up to 30% faster clock performance.
Designers are adopting an HDL verification methodology to help detect errors early in the design cycle. Alliance Series 1.5 includes a evaluation copy of
Get up to 25% higher productivity using an HDL simulator. At gate densities above 10K this becomes more critical. At 60K simulation becomes essential. MTI ModelSim to help you gain more productivity and get to market faster.

5. Performance Based Design Timing Driven Technology
Maximum Device Performance
Achieve max design performance: AKAspeedtm technology
Robust timing constraints language, SMARTspecs
40% Higher Performance with the Floorplanner
Xilinx Core Generator
Industry’s Fastest Devices
Highest Area Utilization Available
> 95% Device Utilization
Flexibility
Freedom to choose the most cost effective device
Design changes with repeatable performance
Performance based design tools are built upon a foundation of timing driven technology with the industries most robust timing constraints language SMARTspecs.
Designers can add their knowledge of the designs structure to increase the performance by using the graphical floorplanner. (Supports XC4000E/X and Spartan). With future support for Virtex.
Xilinx Core Generator is included with the Alliance Series software to help you achieve the highest design performance.
All of this plus the industries fastest devices.
Algorithm advancement in the place and route helps to achieve 95% to 100% device utilization while meeting your performance requirements.
Highest performance and device utilization gives you the flexibility to choose the most cost effective devices. Flexible devices and flexible software allows you to choose a smaller part or cheaper speed grade. 4

6. Achieve Maximum Performance with AKAspeedtm Technology
Minimum delays
Voltage and temperature prorating
Graphical constraints editor
Graphical Floorplanner
Integration with CORE Generator
New Algorithms
Features
Timing-driven implementation K-paths
Advanced timing analysis algorithms
Robust timing language
Incremental Designing
Cores
Enhancements to v1.4
AKAspeedtm Technology – Expect more performance Achieve higher performance with a new suite of advanced algorithms and features. Highlights of AKAspeedtm Technology include: Graphical Constraints Editor, Minimum Delays, Timing-driven Implementation, Robust Timing Language, Incremental Designing and integration with Xiliinx’s Core Generator.
Optimized for Today’s
Higher Performance
Higher Density Designs

7. Flexibility Provides a Productivity Edge
Freedom to choose the most cost effective device
Design changes with repeatable performance
Easy to track design change with revision control
Instant software access with registration-based security
Extensive Platform/OS Support
Win95, WinNT 4.0, NEC PC98
Chinese, Korean & Japanese Windows
Solaris 2.5 & 2.6, HP-UX 10.2, IBM RS6000 AIX 4.1.5
CDE
Revision Control - This is something that Altera does not have. Emphasizing the tool’s ease-of-use and high performance attributes, the Alliance Series 1.5 added the design revision control feature to the Design Manager.
Registration-Based Security saves you time. Register at your convenience. New customers can start designing instantly. No need to call customer service for license. This is something that Altera does not have.
Xilinx’s OS support of EDA tools will coincide with its EDA partners’ platform support strategies. 5

8. Constraint Entry Made Easier
Enter timing constraints into an easy to use Constraints Editor versus this:
NET ClkNet_1 TNM = clk50Mhz;
NET ClkNet_2 TNM = clk20Mhz;
TIMESPEC TS01 = PERIOD:clk50Mhz:20;
TIMESPEC TS02 = PERIOD:clk20Mhz:50;
OFFSET = IN:8:BEFORE:ClkNet_1;
OFFSET = OUT:12:AFTER:ClkNet_1;
Just fill in the blanks.
Constrain an entire design on one simple screen. Guides user toward best constraint methodology. Eliminates need for user knowledge of syntax. Reduces need for user knowledge of nets and components of the design.The benefits are shorter learning curve, easier to set timing constraints and quicker first design.
This is something that Altera does not have
Guides user to the best constraint methodology
Eliminates need for user knowledge of syntax
Reduces need for user knowledge of design nets & components 6

9. Floorplanner
Specify physical placement to reduce routing delays & increase performance up to 40%
Area constraints for modules provide
faster runtimes
higher performance
design changes made easier
The choice to use the floorplanner is a design methodology decision. The Xilinx implementation floorplanner allows users to add his/her knowledge of the designs structure to increase the designs performances by as much as 40%. The Floorplanner supports the XC4000E/X and Spartan devices with future support for Virtex. (No support for XC3x00A/L and XC5200). 7

10. Web-enabled Design Tools
Integrated into Design Manager
Instant Access to
Netscape and MS Explorer compatible
News Bulletins
Searchable Knowledge Base (includes agent reports)
Completely compatible with the browser of your choice release 1.5i is the first stage in making this environment interactive. Integrated into the Project Manager of our Foundation Series and the Design Manager of the Alliance Series is a feature that enables instant access to a designer centric landing zone on the web support.xilinx.com, our design centric web pages.
Simply by selecting this menu item designers are easily and immediately in touch with application notes, the databook, IP and more.
Designer Tools & Services

11. Device Implementation
Alliance Series Flow
Schematics
HDL
Cores
Simulation
Powerful yet simple HDL design flow
Fits into ASIC flow
Enables multiple sources & multiple EDA vendors in the same flow
Simulate anywhere in the design flow
Design the way you are used to!
EDIF, VHDL
Verilog, SDF
Simulation
Synthesis
Simulation
Device Implementation
The Alliance Series software system provides a complete set of powerful, fully- integrated development tools that work seamlessly within your chosen EDA environment. It gives you a complete design solution for Xilinx devices integrating with the familiar industry standard tools and allows you to create designs using a mixture of schematics, High-Level Design Languages (HDL), and predefined modules (intellectual property).
The Xilinx Alliance Series is designed to fit the ASIC design methodology. There is no need to learn a different design flow. Adoption of the industry standard netlists (VHDL, Verilog, EDIF, etc.) enables the Alliance Series system to provide prompt and up-to-date support of the new EDA design tools. In addition, you have complete design flexibility and mixed-vendor support as well as design portability and reuse.
Through the Xilinx Alliance program, leading EDA partners and additional 57 vendors are supported. This wide range of vendor support allows you to design the way you are used to!
Xilinx provides a complete set of HDL and gate-level simulation libraries allowing you to simulate anywhere in the design flow including pre-synthesis, post-synthesis, pre-implementation and post-implementation. 8

12. The Value of Partnerships The most comprehensive “Open System” solution
Early software support for new devices
New product development maximizing architectural and synthesis capabilities
Efficient timing constraints integration
High performance optimization engines tuned for new Xilinx devices
Direct optimization & mapping of Carry logic, complex I/O, LUTs, CE, arithmetic operator
Joint definition of next-generation design flows and technology
Leading Open System Software Solution
Through joint technical teams, Xilinx in conjunction with our EDA partners provide software support for our NEW devices prior to first silicon. This gives designers a jump on designing in a new architecture. They can ‘try out’ a new device even before the silicon is available.
Keeping up with the latest software advancements is in integral part of delivering state-of-the art solutions that achieve the highest speeds, the highest densities, and the fastest time-to-market. The success of the Alliance program and our partners can be attributed to Xilinx’s large dedicated technical and marketing staff. Our close working relationships and commitments have produced high quality synthesis tools. These tools achieve high performance by using algorithms optimized for Xilinx FPGA/CPLD architectures and by mapping directly to the Xilinx device features such as carry logic, LUTs, and complex I/Os.
With Xilinx expertise synthesis vendors continue to improve performance while reducing compile times.

13. HDL Verification We will take you to the leaders
Why simulate?
Reduce time-to-market 25%
Errors early in the design cycle (RTL) are inexpensive to fix
Bottom up and team design for large designs require each module to be verified
It takes twice as long to isolate a bug in hardware than in simulation
Xilinx will take you to the leaders
Visit our HDL Verification Website for our premier partners, articles & design guides
An error, if detected early in the design cycle, during RTL simulation, is fairly inexpensive to fix. However, the cost of fixing the same error increases significantly if the error is caught late in the design since it may involve redesign and re-verification.
An error detected when the product is in the field may take days or even months to isolate and may result in a very expensive product re-call and re-design.
Why Xilinx?
Strong relationship with leading HDL simulation vendors like MTI, Synopsys and Cadence
Early support for industry standards like VITAL, VHDL, Verilog, EDIF and SDF
Minimum delay characterization for hold time and race condition checks
Global-Set-Reset (GSR) simulation models that depict the true behavior in silicon.

14. Cores are essential to High Density Designs
High Performance Reduce Design Time
Cores are essential to High Density Designs
General purpose delivery vehicle for IP
Predictable & repeatable
Independent of device size
Constant performance as more cores are added
Advance specification
Compatible with HDL Design Flows
Custom
Design
Bus
Interface
Memory
DMA
Module
App
Specific
Module
Included with Alliance Series
The Xilinx CORE Generator is a software tool for generating and delivering parameterizable cores optimized for Xilinx FPGAs. Use the CORE Generator to design high-density Xilinx FPGA devices and achieve higher performance results plus a reduction in design time.
CORE Generator Benefits
Faster time-to-market
Fast core generation time with proprietary Xilinx software
Reduced place and route time with pre-placed Cores
Less engineering required with pre-designed cores
Facilitates design reuse
Build your design out of cores
Simpler documentation with larger parameterizable building blocks
Optimal core layout produces lower power dissipation
Processor 12

15. Alliance Series Leading Xilinx into Year 2000
Alliance Future
New Device Families
Reduced Runtimes
Ease of Use
Enhanced Synthesis QOR
Core Generator Enhancements
Modular & Team Design Enhancements
Guide for Synthesis
HDL + Cores + ASIC tools 2M Gates
Features and Enhancements
Alliance 2.1
New Device Families
Reduced Runtimes
Ease of Use
Enhanced Synthesis QOR & Flows
Modular & Team Design
Guide for Synthesis
Enhanced Core Generator Integration
Improved HDL Verification Flows
System Verification Support
HDL + Cores + ASIC tools 1M Gates
In the next release of the Alliance Series (Q199) will include support for new IC architectures. Furthering the support for higher density designs, Xilinx IP solutions will be enhanced as well as modular and iterative design capability will be added. We will enhance the support for system level verification tools such as QUAD Motive (Blast) and LMG SmartModels.
In a future release, the Alliance Series software will continue to support the next generation high performance, high-speed devices. The runtimes will continue to be reduced dramatically along with enhancements to performance in both synthesis tools and implementation. Tools required for higher density designs will be added as well as enhancements to modular and iterative designing in a HDL environment. 14

16. Software that Makes a Difference
Base Configurations
$95!
DS-ALI-BAS-PC
$495
DS-ALI-BAS-WS
$750
Standard Configurations
DS-ALI-STD-PC
$3995
Xilinx offers two Alliance Series products.
BASE with the capability to implement a design up to 10,000 gates and
STANDARD with full device density support. Up to 250K gates.
The BASE system was expanded to support 20,000- system gates + all Spartan devices from 20,000 system gates.
You can purchase the Alliance BASE PC for $95 or try a free Evaluation Kit. (No hardware cables are included.)
DS-ALI-STD-WS
$5995
Software Support
Maintenance
Upgrade Options
Choice Path
Evaluation
DS-ALI-EVAL 15

17. Appendix

18. Core Delivery Mechanism, In Your Flow
SystemLINX
Call the CORE Generator
from third-party tools
Access more Cores
from our Partners
Data sheets
CoreLINX:
Download new cores
from the WEB!
SystemLINX allows you to call the Xilinx Core Generator from 3rd party tools such as Elanix, Matlab and Cadence Alta. This allows DSP designers to design the way the are use to (C+).
CoreLINX allows you to download new cores from the WEB. This allows you to gain access to new cores asynchronously from the Core Generator delivery vehicle.
AllianceCORE allows you to access Cores from our 3rd party suppliers including application notes and sample designs.
LogiCOREs products are pre-implemented and verified system level logic functions sold and supported directly by Xilinx. Including reference designs and application notes.
Standard Bus Interfaces - such as PCI, PCMCIA, USB and IIC.
DSP Functions - These range from small building blocks such adders, registers and multipliers, to larger system-level functions such as FIR filters and transforms.
Communications and Networking - such as HDLC, T1 framers and ATM functions.
Base-Level Functions - a broad category of functions used across many application segments. These include the very small parameterizable LogiBLOX macros up through larger functions such as UARTs and RISC processors.
Cores available from Xilinx
DSP, PCI, general purpose 17

19. CPLD Implementation Flow
Simplified Project Management
Implementation Templates for Speed & Density
Push Button Design Flows
Whether you choose the Alliance Series, Xilinx offers an easy-to-use implementation flow for CPLD designs.
With simplified, easy to understand project management coupled with intuitive push button flows, a CPLD designer can navigate their design from netlist entry to JEDEC programming file in minutes.
Pre-defined implementation templates allow the user to quickly target, or retarget, their design to best fit their current objectives.
Continuing enhancements in both fitting technology algorithms and compile time directives give designers faster system clock speeds, faster compile times, higher device utilization and maintains the industry’s best pin-locking solution!
Performance algorithm enhancements ensure faster clock speeds,higher device utilization and the industry’s best pin-locking capabilities!