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Xilinx CPLD Fitter Advanced Optimization

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Presentation on theme: "Xilinx CPLD Fitter Advanced Optimization"— Presentation transcript:

1 Xilinx CPLD Fitter Advanced Optimization

2 CPLD Training Course Optimizing for Speed and Density

3 Objectives Understand the capabilities of the Advanced Optimization Tab in the Implementation Options dialog box Learn good strategies for optimizing designs for speed and density

4 Agenda Parallel and Series Logic Optimizing for Speed
Optimizing for Density Examples Optimize Speed and Density Templates Summary

5 Parallel Logic Borrowed Pterms Macrocell Pterms
D/T Macrocell Pterms Parallel logic occurs when the Fitter maximizes the use of the Product Term Allocator (also referred to as Flattening) Parallel logic improves the performance of a design by reducing the number of levels of logic required However, this also effectively groups logic together in the same function block Grouping logic can decrease the utilization of any function block Parallel logic usually requires a large number of the function block inputs

6 Series Logic Feedback Feedback D/T Macrocell Pterms Macrocell Pterms Macrocell Pterms Series logic borrows very few product terms from the Product Term Allocator (also referred to as deepening) Series logic is easy to fit inside an XC9500/XL device because it does not borrow much logic Series logic requires multiple levels of combinatorial logic These pieces are slower than Parallel logic since they use more feedback resources

7 Advanced Tab Collapsing Product Term Limit Collapsing Input Limit
Controls collapsing of multi-level logic. Multi-level logic is flattened until the product term limit is reached. Raising limit can increase speed at expense of density Has no effect (set to 90) during density optimization Collapsing Input Limit Controls collapsing of multilevel logic. Multi-level logic is collapsed until input limit is reached Lowering limit can improve density at expense of speed Default limit is equal to the maximum number of function block inputs in the device

8 Creating Parallel Logic
Higher speed is often desired Remember the trade-offs Flatter designs tend to be created when the following principals are adhered to Don’t over-constrain Set limits to the proper level Use timing optimization

9 Timing Constraints Timing Constraints effectively communicate performance expectations to the compiler Use global constraints as a “quick and dirty” way of getting the speed necessary Do not over constrain the design Use signal specific constraints to fine tune the performance Allows software to make informed product term allocation and logic collapsing decisions Assert the Use Timing Constraints option, otherwise constraints will be ignored Constraints permit the optimization of some paths and not others, which gives the tools more flexibility

10 Increase the Pterm Limit
Increase the Product Term Collapsing Limit Increases the flattening of multi-level logic by using product term allocator feature This uses the faster interconnect between product term allocators Raise from 20 (default) to 45 or even 90 (FB pterm limit) Check the Fitting Report to determine the extent to which product terms are being borrowed Assert the Use Timing Optimization option Useful for designs that contain multi-level logic or speed critical signals This option tends to improve slowest paths, whereas constrained paths specify which paths to improve

11 Creating Series Logic Higher density is often desired
Remember the trade-offs Deep designs tend to be created when the following principals are adhered to Don’t over-constrain locations Set limits to the proper level Use advanced fitting option

12 Reduce the Creation of Parallel Logic
Creation of Parallel logic occurs when the Product Term Allocator is used extensively Decrease the Collapsing Pterm Limit to map the logic into smaller chunks (force more feedback) Decrease the Collapsing Input Limit to reduce the amount of logic in some function blocks

13 Use the Advanced Fitting Option
This is a different partitioning algorithm that places functions that share inputs into the same function block Use this option if the design becomes function block input limited The Advanced Fitting option will not impact performance This option is on by default

14 Use the KEEP Attribute Use this attribute on high fanout product terms or input intensive nodes Overrides product term and function block input collapsing limits in GUI Boolean logic reduction still performed KEEP 12 Product Term Implementation 6 Product Term Implementation

15 Global Resources (The Highest Payoff for Speed and Density)
Use global control signals Using global clock, output enable and set/reset nets saves function block inputs and local product terms Assign high fanout control signals generated in macrocells to global nets FF0 FF5 FF6 FF7 FF8 FF1 FF2 FF3 FF4 BUFG=OE

16 Function Block Input Limited Design
******** Resources Required By Unmapped Logic and Pins*********** ** Logic Signal Total Signals Pwr Slew Name PT Used Mode Rate EXIT STD DPCS STD IO STD LBE STD SP STD **************** Function Block Resource Summary **************** Function # of FB Inputs Signals Total O/IO IO Block MCells Used Used PT Used Req Avail FB /0 17 FB /0 17 FB /1 17 FB /0 17 FB /1 17 FB /0 16 FB /1 16 FB /3 16 /6 133

17 Solution First, use the Advanced Fitting option
**************** Function Block Resource Summary **************** Function # of FB Inputs Signals Total O/IO IO Block MCells Used Used PT Used Req Avail FB /0 17 FB /0 17 FB /1 17 FB /0 17 FB /1 17 FB /0 16 FB /1 16 FB /3 16 /6 133 First, use the Advanced Fitting option If no improvement is seen, gradually reduce the function block input collapse limit to reduce the creation of parallel logic Macrocell count increases when collapse limit decreases

18 Product Term Limited Design
******** Resources Required By Unmapped Logic and Pins*********** ** Logic Signal Total Signals Pwr Slew Name PT Used Mode Rate EXIT STD DPCS STD IO STD LBE STD SP STD **************** Function Block Resource Summary **************** Function # of FB Inputs Signals Total O/IO IO Block MCells Used Used PT Used Req Avail FB /0 17 FB /0 17 FB /1 17 FB /0 17 FB /1 17 FB /0 16 FB /1 16 FB /3 16 /6 133

19 Solution Gradually reduce the Product Term Collapse Limit
**************** Function Block Resource Summary **************** Function # of FB Inputs Signals Total O/IO IO Block MCells Used Used PT Used Req Avail FB /0 17 FB /0 17 FB /1 17 FB /0 17 FB /1 17 FB /0 16 FB /1 16 FB /3 16 /6 133 Gradually reduce the Product Term Collapse Limit The number of macrocells used will increase

20 Function Block and Product Term Limited
******** Resources Required By Unmapped Logic and Pins*********** ** Logic Signal Total Signals Pwr Slew Name PT Used Mode Rate EXIT STD DPCS STD IO STD LBE STD SP STD **************** Function Block Resource Summary **************** Function # of FB Inputs Signals Total O/IO IO Block MCells Used Used PT Used Req Avail FB /0 17 FB /0 17 FB /1 17 FB /0 17 FB /1 17 FB /0 16 FB /1 16 FB /3 16 /6 133

21 Solution First, use the Advanced Fitting option
**************** Function Block Resource Summary **************** Function # of FB Inputs Signals Total O/IO IO Block MCells Used Used PT Used Req Avail FB /0 17 FB /0 17 FB /1 17 FB /0 17 FB /1 17 FB /0 16 FB /1 16 FB /3 16 /6 133 First, use the Advanced Fitting option Second, fit the design with Timing Optimization OFF Third, reduce the FB Input Collapse Limit Number of macrocells will increase Finally, reduce the Product Term Collapse Limit

22 Choosing New Product Term Limit
******** Resources Used by Successfully Mapped Logic ************ Signal Total Signals Loc PWR Slew Pin Name PT Used Mode Rate # Q0 1 8 FB7_5 STD FAST 19 Q1 5 7 FB3_1 STD FAST 35 Q FB6_5 STD FAST 75 Q2 7 3 FB3_1 STD FAST 160 Q FB5_8 STD FAST 100 ******** Resources Required By Unmapped Logic and Pins*********** ** Logic Signal Total Signals Pwr Slew Name PT Used Mode Rate EXIT STD DPCS STD IO STD LBE STD SP STD Reduce limits below requirements of largest implemented equations

23 Summary Timing Constraints are the most effective way to obtain good performance Raising the Product Term Collapsing Limit increases the creation of Parallel logic, which improves the performance of some designs Use of Global Resources frees Product Terms for use. This gives payoff in speed and density Reducing the Product Term Collapsing Limit will reduce the performance of some modules, but will improve the density Use the KEEP attribute to save product terms on high fanout nets

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