1. Ch.9 CPLD/FPGA Design TAIST ICTES Program VLSI Design Methodology Hiroaki Kunieda Tokyo Institute of Technology

2. 2 Outline 1. CPLD & FPGA 2. Design Procedure

3. 9.1 Programmable Device

4. 4 FPGA Reconfigurable LSI or Programmable Hardware Programmable Logic Array and Programmable Interconnection Programmed by Reconfigurable Data Xilinx and Altera Prototyping of ASIC (different physical condition)

5. ECE 545 – Introduction to VHDL The Programmable Marketplace The Programmable Marketplace Q1 Calendar Year 2005 Source: Company reports Latest information available; computed on a 4-quarter rolling basis Xilinx Altera Lattice Actel QuickLogic: 2% Xilinx All Others Two dominant suppliers, indicating a maturing market PLD SegmentFPGA Sub-Segment Other: 2% 51% 33% 5% 7% Altera 58% 31% 11%

6. ECE 545 – Introduction to VHDL FPGA families Spartan 3 Virtex 4 LX / SX / FX Spartan 3E Virtex 5 LX Spartan 3L Low-costHigh-performance Xilinx Altera Cyclone II Stratix II Stratix II GX

7. Xilinx and Altera FPGA Xilinx#gatesProgramClockNote Virtex50k-10MSRAM550MHzSystem Spartan5k-300kSRAM250MHzASIC XC950013k-85kSRAM100MHz Altera#gatesProgramClockNote Stratix 180kSRAM500MHzHigh end RAM & Multiplier Cyclone 16kSRAM200MHzLow cost FLEX 10k-250kSRAM200MHzHigh Speed MAX(CPLD) 600-10KEEPROM150MHzLow Price

8. 9.2 PLD

9. 9 ＣＰＬＤ

10. Function Block in CPLD

11. Example of PLD Design S １ S ２ S ３ X S １ S ２ S ３ Y 0 0 0 0 0 10 0 1 0 0 0 1 *0 1 1 0 0 1 1 *1 1 1 0 1 1 1 *1 1 0 0 1 1 0 *1 0 0 0 1 0 0 *0 0 0 1 000 001 011 111 110 100 X=0 X=1 State Transition Table Y=1

12. PLA & FF Realization S １ S ２ S ３ X DS １ DS ２ DS ３ Y 0 0 0 0 0 10 0 1 0 0 0 1 *0 1 1 0 0 1 1 *1 1 1 0 1 1 1 *1 1 0 0 1 1 0 *1 0 0 0 1 0 0 *0 0 0 1 S1 DS1 PLA AND-OR S2 DS2 S3 DS3 X Y DFF

13. 9.3 FPGA

14. ECE 545 – Introduction to VHDL Block RAMs Configurable Logic Blocks I/O Blocks Xilinx FPGA Block RAMs

15. ECE 545 – Introduction to VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Xilinx CLB

16. LUT

17. LUT Structure

18. Interconnection Logic Block

19. 19 Advantages and Disadvantages Advantages Short TAT(Turn-Around Time) Small NRE (Non Recurrent Expense) Fee Logic and Timing Design are required. Full amount of IP (Intellectual Property) Disadvantages Slow speed and Large Chip Area High cost for volume manufacturing

20. 9.4 FPGA Design

21. FPGA Design Functional Verification Logic Synthesis RTL Simulation RTL Synthesis Netlist Gate Assignment LE Place and Rout Configuration Data FPGA Tool LSI Tool

22. FPGA Design Flow

23. １ bit Adder/Subtracter

24. 4bit Adder/Subtracter

25. FPGA Design

26. Three-Step Design Compilation in Quartus II Software 1. Run the New Project Wizard a. Specify project directory, name, and top-level entity. b. Specify project design files. c. Specify Altera device family for the design. d. Specify device (or specify device information for automatic device selection). e. Specify other EDA tools to be used for this project. f. Review project settings.

27. 2. Run the TimeQuest Timing Analyzer a. On the Process menu, click Start Analysis & Synthesis to build a netlist in preparation for TimeQuest timing analyzer use. b. On the Tools menu, click TimeQuest Timing Analyzer to launch TimeQuest analyzer. i. On the Netlist menu, click Create Timing Netlist and select Post- map to create the timing netlist with timing delay information. ii. Specify your design timing constraints using the analyzer’s graphical user interface (GUI) or by using the Synopsys Design Constraint (SDC) text editor. c. On the Assignment menu, click Timing Analysis Settings to specify TimeQuest analyzer as the timing analysis tool and to add your SDC file to the project. Quartus II Assignment menu provides all settings and assignments for the project.

28. 3. Compile the Design a. Select one of the following methods to compile the design: i. On the Processing menu, click Start Compilation. ii. On the menu toolbar, click. iii. On the Processing menu, click Compiler Tool and click Start. b. When compilation is complete, refer to the Compilation Report window to view information on compiler settings, resource usage, and compilation equations. Timing analysis is also performed during compilation on the current design, and the Compilation Report window includes the timing information.

29. 9.5 Optimization

30. Trade-offs speedarea power testability

31. Speed optimization (1) better architecture (e.g., CLA vs. ripple carry adder) pipelining parallel processing optimization options of synthesis and implementation tools

32. ECE 545 – Introduction to VHDL Speed optimization (2) reducing fanout of control signals better state encoding registered outputs from the state machine