1. 1 2/1/99 Confidential Selling Xilinx Software vs. Altera Xilinx Academy February 24th, 1999

2. 2 2/1/99 Confidential Volume Requirements By Business Price Density $2/unit500Kunits=$1M$10/unit100Kunits=$1M$100+/unit10Kunits=$1M CPLD High Volume FPGA High Density FPGA

3. 3 2/1/99 Confidential XILINXALTERA vs. FLEX 6K vs.FLEX 10K vs. Raphael vs. MAX PLUS+

4. Xilinx Software How to Compete and Win Against Altera

5. 5 2/1/99 Confidential Xilinx Software  Intuitive Design Environment; Easy to Use  Superior HDL Design Solutions  Best Push-Button Results plus Performance Driven “When You Need it”  Best Value Software Configurations

6. 6 2/1/99 Confidential Xilinx Software  Intuitive Design Environment; Easy to Use Superior HDL Design Solutions  Superior HDL Design Solutions  Best Push-Button Results plus Performance Driven “When You Need it”  Best Value Software Configurations

7. 7 2/1/99 Confidential Xilinx Ease-of-Use Push Button Design Flows Design Wizards Graphical State Diagram Entry High Volume Solution Interactive Web Enabled Software Xilinx Altera 4 4 Very Limited 4 NO! 4 Limited Device Support Proprietary Synthesis 4 NO!

8. 8 2/1/99 Confidential Xilinx Software  World-Class EDA Technology, Intuitive Design Environment  Superior HDL Design Solutions  Best Push-Button Results plus Performance Driven “When You Need it”  Best Value Software Configurations

9. 9 2/1/99 Confidential 4 4 4 4 4 Express Feature Xilinx HDL Centric Project Management Synopsys Synthesis VHDL and Verilog Included Synthesis Constraint Entry & Timing Analysis Robust Language Support Altera NO! Choose 1 NO!

10. 1010 2/1/99 Confidential Xilinx Software  World-Class EDA Technology, Intuitive Design Environment  Superior HDL Design Solutions  Best Push-Button Results plus Performance Driven “ When You Need It”  Best Value Software Configurations

11. 1 2/1/99 Confidential Push-Button Design Runtime in MinutesPerformance in MHz  20 HDL designs ranging from 5K to 100K gates  XC4000XL-08 vs. 10KA-1, Alliance Series 1.5 vs. Max+PLUS II v9.01  Runtimes are place and route only on 400MHz Pentium II 3% 9% 42% 44% 4% Default

12. 1212 2/1/99 Confidential 4 4 4 4 4 Performance Driven Design Xilinx Temp / Voltage Prorating Robust Constraints Language Floorplanner Min Timing Robust Timing Reports Altera NO! 4 4 Revision Control NO!

13. 1313 2/1/99 Confidential Xilinx Software  World-Class EDA Technology, Intuitive Design Environment  Superior HDL Design Solutions  Best Push-Button Results plus Performance Driven “ When You Need It”  Best Value Software Configurations

14. 1414 2/1/99 Confidential Volume Requirements By Business Price Density $2/unit500Kunits=$1M$10/unit100Kunits=$1M$100+/unit10Kunits=$1M CPLD High Volume FPGA High Density FPGA

15. 1515 2/1/99 Confidential Target Markets / SolutionsPrice Density CPLD High-VolumeFPGA High-EndFPGA FND-BSX FND-EXP ALI-STD $4,995! $4,995! FND-BAS $95, $495 $95, $495 FND-BSX $495! $495!

16. 1616 2/1/99 Confidential 4 4 PLS-ES / PLS-WEB F1.5 vs. Max+plus II 9.0 Entry Level Software FND-BAS / Free download from Web Proprietary AHDL Synthesis No VHDL / Verilog Synthesis No Simulation No FPGAs, No 6K or 9K Support Free Site-License after PLS- BASE purchase ($995) 4 4 4 4 NEW WebFitter XABEL Synthesis (BAS) VHDL/Verilog Synth (WebFitter) Functional & Timing Simulation CPLDs & High Volume FPGAs included! $95 4 4

17. 1717 2/1/99 Confidential 4 4 4 4 4 4 4 Synopsys Synthesis VHDL and Verilog HDL Support Best Push-Button Results (Non-TD, Same Constraint TD) A.K.A. Speed Technology Complete CPLD and High Volume FPGA Support Functional & Timing Simulation $495 PLS-BASE F1.5 vs. Max+plus II 9.0 High Volume Software FND-BSX Proprietary Synthesis Choose One Best Push-Button Results (Non-TD, Same Constraint TD) Basic Timing Driven Tech. 6K, 9K, Timing Driven Optional Functional Simulation Only $995 + $995 ea. PLSM-6K/8K & PLSM-9K Migration Options 4 4

18. 1818 2/1/99 Confidential 4 4 4 4 4 4 4 4 Synopsys Synthesis VHDL and Verilog HDL Support Best Timing Driven Results A.K.A. Speed Technology HDL Centric Project Mgmt Revision Control Joint Development for Next Generation Flows $3995 ALI-STD / $4995 FND-EXP PLS-MAGNUM F1.5 vs. Max+plus II 9.0 High End FPGA Software FND-EXP Proprietary Synthesis Choose One Inferior TD Results Basic Timing Driven Tech. Basic Project Management Focus on Proprietary Synth $4,995 4 ALI-STD 4

19. 1919 2/1/99 Confidential  Mainstream designer Productivity is dependent on: —Ease-of-Use —Run Time  High density and high speed designer Productivity is dependent on: —User Control —Design Performance —Design Iteration Time - Run Time Where Is The Value In Software? Customers see value in software that will enable them to get their job done in the fastest possible time. Productivity through: Ease-of-Use Performance Driven Design User Control.

20. 2020 2/1/99 Confidential Where’s the Value in 1.5? Ease of Use  Constraints Editor —Simple control over powerful constraints  Automatic Pin Locking —When you’re ready for board layout  Improved Reporting —Important information first

21. 2121 2/1/99 Confidential Guides user to the best constraint methodology Graphical Constraints Editor

22. 2 2/1/99 Confidential  Minimum Delays  Temperature and Voltage Prorating —Faster performance at more optimal operating conditions  Dramatic Improvements to PAR Where’s the Value in 1.5? Performance

23. 2323 2/1/99 Confidential  Average 2-3x runtime improvement, 10x on some designs  Faster timing analysis with K-path algorithm  Achieves higher clock rates more easily All this means…. More Turns Per Day Faster Design Cycles Where’s the Value in 1.5? Performance - PAR Improvements

24. 2424 2/1/99 Confidential  Floorplanner  New Constraints  Push Button Performance —Simple control over tradeoff between runtime and performance Where’s the Value in 1.5? User Control

25. 2525 2/1/99 Confidential Foundation & Alliance Series Unparalleled Productivity Key Features in Version 1.5  4 New FPGA/CPLD Families  50% Runtime Reduction  Graphical Constraints Editor  Floorplanner  Automatic Pin Locking  6x Faster Timing Analysis (Kpaths algorithm)  New Reporting of Minimum Delays  Voltage and Temperature Speed Pro-rating

26. 2626 2/1/99 Confidential Key Messages For Alliance  Standards Based Design Interfaces Allows customers to work in their chosen EDA environment.  A.K.A. speed tm TECHNOLOGY Faster compile times and increased clock speed lets customers meet their specifications and get their product to market more quickly.  Integrated Core Generator Software And LogiBLOX Customers can achieve higher performance and get their designs done faster.  World Class Technical Support Instant support over the Web and via the phone to assist customers in completing designs.

27. 2727 2/1/99 Confidential Key Messages For Foundation  Complete Front-To-Back Design Environment The tightly integrated tool set makes it easy for customer to learn and use the tools.  Powerful VHDL And Verilog Synthesis - Synopsys FPGA Express Robust language support and optimization technology allows customers to get the most speed out of their design.  Graphical HDL Editor And Integrated Language Wizard Simple graphical tools help to reduce the time it takes for customers to complete their design.  World Class Technical Support Instant support over the Web and via the phone to assist customers in completing designs.