Day 29: November 11, 2013 Memory Core: Part 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 29: November 11, 2013 Memory Core: Part 1 Penn ESE370 Fall2013 -- DeHon

Today 5T SRAM DRAM Writing Charge sharing Precharge Penn ESE370 Fall2013 -- DeHon

Memory Bank Penn ESE370 Fall2013 -- DeHon

5T SRAM Memory Bit Penn ESE370 Fall2012 -- DeHon

Write (preclass 1) Assuming properly select only one WL, what does write circuit look like? What transistors are ON when writing a 0 over a cell that holds a 1? Drive with inverter at BL Width Wwrite Voltage written? 1V Penn ESE370 Fall2013 -- DeHon

Write (preclass 1) Assuming properly select only one WL, what does write circuit look like? Voltage written? 1V Penn ESE370 Fall2013 -- DeHon

Write Conclude? Writing into cell is a ratioed operation. Penn ESE370 Fall2013 -- DeHon

Preclass 2 Initially Close switch Voltage at A? A @ 1V B @ 0V Penn ESE370 Fall2013 -- DeHon

Preclass 2 Initially QA=1V*C1=C1 Close switch Qtot=Vfinal*(C1+C0) B @ 0V QA=1V*C1=C1 Close switch Qtot=Vfinal*(C1+C0) Charge conservation QA=Qtot C1=Vfinal*(C1+C0) Penn ESE370 Fall2013 -- DeHon

Consider (preclass 3) Read: What happens to voltage at A when WL turns from 01? Assume Waccess large Waccess >> Wpu=1 BL initially 0 A initially 1 Penn ESE370 Fall2013 -- DeHon

Voltage After enable Word Line QBL = 0 QA = (1V)(g(2+Waccess)C0) CBL>>CA=(g(2+Waccess)C0) After enable Waccess (Waccess large) Total charge QBL +QA roughly unchanged Distributed over larger capacitance~=CBL VA=VBL~= CA/CBL Penn ESE370 Fall2013 -- DeHon

Larger Resistance? What happens if Waccess small? Waccess < Wpu Penn ESE370 Fall2013 -- DeHon

Larger Resistance? What happens if Waccess small? Waccess < Wpu Takes time to move charge from A to BL Moves more slowly than replished by pu Penn ESE370 Fall2013 -- DeHon

Simulation: Waccess=100 Penn ESE370 Fall2013 -- DeHon

Simulation Penn ESE370 Fall2013 -- DeHon

Charge Sharing Conclude: charge sharing can pull down voltage Penn ESE370 Fall2013 -- DeHon

Consider What happens to voltage at A when WL turns from 01? Assume Waccess large Penn ESE370 Fall2013 -- DeHon

Simulation Waccess=20 Penn ESE370 Fall2013 -- DeHon

Simulation Waccess=4 Penn ESE370 Fall2013 -- DeHon

Charge Sharing Conclude: charge sharing can lead to read upset Charge redistribution adequate to flip state of bit Penn ESE370 Fall2013 -- DeHon

How might we avoid? Penn ESE370 Fall2013 -- DeHon

Charge to middle Voltage Charge bitlines to Vdd/2 before begin read operation Now charge sharing doesn’t swing to opposite side of midpoint Penn ESE370 Fall2013 -- DeHon

Pre-Charge Use one phase of clock to charge a node to some initial value before operation Precharge Transistor Can be large Penn ESE370 Fall2013 -- DeHon

Pre-Charge Use one phase of clock to charge a node to some initial value before operation Precharge Transistor Can be large Penn ESE370 Fall2013 -- DeHon

Simulation Waccess=20 Penn ESE370 Fall2013 -- DeHon

Compare Both Waccess=20; vary precharge Penn ESE370 Fall2013 -- DeHon

5T SRAM Questions? Penn ESE370 Fall2013 -- DeHon

DRAM Penn ESE370 Fall2013 -- DeHon

1T 1C DRAM Simplest case – Memory is capacitor Feature of DRAM process is ability to make large capacitor compactly Penn ESE370 Fall2013 -- DeHon

1T DRAM What happens when read this cell? Cbit << Cbl Penn ESE370 Fall2013 -- DeHon

1T DRAM On read, charge sharing Small swing on bit line VBL = (Cbit/CBL)Vstore Small swing on bit line Must be able to detect Means want large Cbit limit bits/bitline so VBL large enough Cell always depleted on read Must be rewritten Penn ESE370 Fall2013 -- DeHon

Dynamic RAM Takes sharing idea one step further Share refresh/restoration logic as well Only left with access transistor and capacitor Penn ESE370 Fall2013 -- DeHon

3T DRAM Penn ESE370 Fall2013 -- DeHon

3T DRAM How does this work? Write? Read? Penn ESE370 Fall2013 -- DeHon

3T DRAM Correct operation not sensitive to sizing Does not deplete cell on read No charge sharing with stored state All NMOS (single well) Prechage ReadData Must use Vdd+VTN on W to write full voltage Penn ESE370 Fall2013 -- DeHon

Some Numbers (memory) Register as stand-alone element (14T)  4Kl2 Static RAM cell (6T)  1Kl2 SRAM Memory (single ported) Dynamic RAM cell (DRAM process)  100l2 Dynamic RAM cell (SRAM process)  300l2 Penn ESE370 Fall2013 -- DeHon

Idea Memory can be compact Rich design space Demands careful sizing Penn ESE370 Fall2013 -- DeHon

Admin Midterm2 solutions HW7 due tomorrow Project 2 out Now updated with problem 2 pix HW7 due tomorrow Project 2 out Due 2 weeks from tomorrow Tuesday before Thanksgiving Penn ESE370 Fall2013 -- DeHon