FACTORY LOT STATUS - MESA

Slides:



Advertisements
Similar presentations
SOFI R EVIEW M EETING - C ONFIDENTIAL 1 CONFIDENTIAL SOFI : WP3 - Silicon Chips SOFI meeting – 20 January Rome.
Advertisements

CMOS Process at a Glance
Trench 3 process flow Discretes and MultiMarket ICs DMI – BL Power 17 july 2002.
Chapter 2 Modern CMOS technology
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 CMOS Process Manufacturing Process.
Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.
School of Microelectronic Engineering EMT362: Microelectronic Fabrication CMOS ISOLATION TECHNOLOGY Part 2 Ramzan Mat Ayub School of Microelectronic Engineering.
Process integration
© March 24, 2008, Dr. Lynn Fuller Gig Ohm Resistors Fabrication Process Page 1 Rochester Institute of Technology Microelectronic Engineering ROCHESTER.
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process I Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated.
Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-1  10 Micrometer Design Rules  4 Design Layers.
ES 176/276 – Section # 2 – 09/19/2011 Brief Overview from Section #1 MEMS = MicroElectroMechanical Systems Micron-scale devices which transduce an environmental.
Click mouse or hit space bar to advance slides All slides property of Cronos, all rights reserved Silicon Substrate Add nitride.
Manufacturing Process
IC Process Integration
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Chapter 2 Manufacturing Process March 7, 2003.
Semiconductor Manufacturing Technology Michael Quirk & Julian Serda © October 2001 by Prentice Hall Chapter 9 IC Fabrication Process Overview.
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated.
Introduction EE1411 Manufacturing Process. EE1412 What is a Semiconductor? Low resistivity => “conductor” High resistivity => “insulator” Intermediate.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 3, slide 1 Introduction to Electronic Circuit Design.
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Digital Integrated Circuits A Design Perspective Manufacturing Process Jan M. Rabaey Anantha Chandrakasan.
IC Fabrication/Process
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING
Digital Integrated Circuits A Design Perspective
Dynamic Behavior of MOS Transistor. The Gate Capacitance t ox n + n + Cross section L Gate oxide x d x d L d Polysilicon gate Top view Gate-bulk overlap.
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING
© June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 1 Rochester Institute of Technology Microelectronic Engineering ROCHESTER.
Plasma bay modernised in Sentech SI 500 RIE cluster Si 3 N 4, SiO 2, polySi and Al etching 2 x Oxford System 100 ICP Si 3 N 4, SiO 2, polySi, polymers,
Side ViewTop View Beginning from a silicon wafer.
EE141 Manufacturing 1 Chapter 2 Manufacturing Process and CMOS Circuit Layout 1 st rev. : March 7, nd rev. : April 10, 2003.
Io School of Microelectronic Engineering Lecture IV B.
(Chapters 29 & 30; good to refresh 20 & 21, too)
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated.
KUKUM – SHRDC INSEP Training Program 2006 School of Microelectronic Engineering Lecture V Thermal Processes.
MOSCAP Characterization of SNF ALD
Lecture 2 State-of-the art of CMOS Technology
Solar Cell and NMOS Transistor Process EE290G Joey Greenspun.
Process integration 2: double sided processing, design rules, measurements
New Mask and vendor for 3D detectors
Process integration 1: cleaning, sheet resistance and resistors, thermal budget, front end
EE 3311/7312 MOSFET Fabrication
CMOS Fabrication CMOS transistors are fabricated on silicon wafer
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING
Process technology Physical layout with L-Edit
Manufacturing Process I
EMT362: Microelectronic Fabrication
Microelectronic Fabrication
CMOS Process Flow.
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING
EMT362: Microelectronic Fabrication CMOS ISOLATION TECHNOLOGY Part 2
NanoFab Simulator Update
VLSI System Design LEC3.1 CMOS FABRICATION REVIEW
Digital Integrated Circuits A Design Perspective
Design and Process Integration
Etch Dry Etch.
Optional Reading: Pierret 4; Hu 3
Add nitride Silicon Substrate.
Lecture #25 OUTLINE Device isolation methods Electrical contacts to Si
Manufacturing Process I
VLSI Lay-out Design.
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING
FEOL Front End Of Line.
V.Navaneethakrishnan Dept. of ECE, CCET
complementary metal–oxide–semiconductor Isolation Technology: Part 2
Standard 16-Mask CMOS Process Overall Structure of CMOS.
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING
Manufacturing Process I
Add nitride Silicon Substrate
Presentation transcript:

FACTORY LOT STATUS - MESA Instructions: Prior to each lab the current lot status is determined to provide information to the students on which lots they should be working on. The students are divided into five different teams given the names of Red, Orange, Yellow, Green an Blue. (see page 5 of this document) Each team works for three week in each of five different process areas. After the third week one of the students in the team give a pass down presentation summarizing what was done in the last three weeks (5 min. max) Teams move to new process areas every three weeks so that be the end of the semester they all add experience in each of the five process areas. The lot status itself is found by logging into MESA and doing lot status of all lots. (option 4 on the main menu) The most recent lot status template is copied and pasted betweem page 5 and 6 of this document. Then changes are made to the most recent lot status page 2 to reflect the current lot status. Change, Date, Current Operation, Q or P, Step Number, Next Operation, Quantity of wafers, Comments. Also move the team color at the top of the template after each three weeks one spot clockwise. Print two pages 2 and 3 only, two slides per page, one for each student. Check equipment status (by talking to equipment engineers) Review the lot status just prior to lab with the students and answer any questions they may have.

Rochester Institute of Technology Microelectronic Engineering Dr. Lynn Fuller Orange (Diffusion) Yellow (Lithography) Green (Plasma Etch) Blue (Implant/CVD) Red (wet Etch) Date: 4-26-18 Lot Status Report Time: 8:00 am Lot No Product Process / Version Current operation Q P STEP Next Operation Qty Comments F150903 JOHN GALT SUB-CMOS 150 TE01 X 77 TE02 3 ORANGE F160218 ET15 75 ET07 2 F160922 ET26 61 BLUE F170126 PH03 42 IM01 YELLOW F170223 F171102 21 F180118 11 OX06 F180208 6 F180322 ET29 5 GREEN RED – TEST working CMOS, NMOS ID-VDS, ID-VG, SUB-VT ORANGE – TEST working pmos

SUB-CMOS 150 PROCESS 2-6-13 SUB-CMOS Versions 150 1. CL01 2. OX05--- pad oxide, Tube 4 3. CV02- Si3N4-1500Å 4. PH03 –1- JG nwell 5. ET29 – Nitride Etch 6. IM01 – n-well 7. ET07 – Resist Strip 8. CL01 9. OX04 – well oxide, Tube 1 10. ET19 – Hot Phos Si3N4 11. IM01 – p-well 12. OX06 – well drive, Tube 1 13. ET06 - Oxide Etch 14. CL01 15. OX05 – pad oxide, Tube 4 16. CV02 – Si3N4 -1500 Å 17. PH03 – 2 – JG Active 18. ET29 – Nitride Etch 19. ET07 – Resist Strip 20. PH03 - -Pwell Stop 21. IM01- stop 22. ET07 Resist Strip 23. CL01 24. OX04 – field, Tube 1 25. ET19 – Hot Phos Si3N4 26. ET06 – Oxide Etch 27. OX04 – Kooi, Tube 1 28. IM01 – Blanket Vt 29. PH03 – 4-PMOS Vt Adjust 30. IM01 - Vt 31. ET07 – Resist Strip 32. ET06 – Oxide Etch 33. CL01 34. OX06 – gate, Tube 4 35. CV01 – Poly 5000A 36. IM01 - dope poly 37. OX08 – Anneal, Tube 3 38. DE01 – 4 pt Probe 39. PH03-5-JG poly 40. ET08 – Poly Etch 41. ET07 – Resist Strip 42. PH03 – 6 - n-LDD 43. IM01 44. ET07 – Resist Strip 45. PH03 – 7 - p-LDD 46. IM01 47. ET07 – Resist Strip 48. CL01 49. CV03 –TEOS, 5000A 50. ET10 - Spacer Etch 51. PH03 – 8 - N+D/S 52. IM01 – N+D/S 53. ET07 – Resist Strip 54. PH03 – 9 P+ D/S 55. IM01 – P+ D/S 56. ET07 – Resist Strip 57. CL01 Special - No HF Dip 58. OX08 – DS Anneal, Tube 2 59. CV03 – TEOS, 5000A 60. PH03 – 10 CC 61. ET26 - CC Etch 62. ET07 – Resist Strip 63. CL01 Special - Two HF Dips 64. ME01 – Metal 1 Dep 65. PH03 -11- metal 66. ET15 – plasma Etch Al 67. ET07 Resist Strip 68. SI01 - Sinter 69. CV03 – TEOS- 5000Å 70. PH03 – VIA 71. ET26 – Via Etch 72. ET07 – Resist Strop 73. ME01 – Metal 2 Dep 74. PH03- M2 75. ET15 – plasma Etch Al 76. ET07 - Resist Strip 77. SEM1 78. TE01 79. TE02 80. TE03 81. TE04 2-6-13

ADV-CMOS 150 PROCESS (Revision 05-02-14) ADV-CMOS Versions 150, Two level Metal 1. OX05--- pad oxide 500 Å, Tube 4 2. CV02- 1500 Å Si3N4 Deposition 3. PH03 – level 1- STI 4. ET29 - etch Nitride 5. ET07 – ash 6. CL01 – RCA clean 7. OX04 – First Oxide Tube 1 8. ET06 – Etch Oxide 9. OX04 – 2nd Oxide Tube 1 10. ET19 – Etch Nitride 11. PH03 – level 2 - N-well 12. IM01 – 5E13, P31, 170 KeV 13. ET07 – ash 14. PH03 – level 3 - P-well 15. IM01 – 7E13, B11, 100 KeV 16. ET07 – ash 17. OX06 – Well Drive, Tube 1 18. PH03 – level 4 - N-well retrograde 19. IM01 – 9E13, P31, 70 KeV 20. ET07 - ash 21. PH03 – level 5 - P-well retrograde 22. IM01 – 1E14, B11, 45 KeV 23. ET07 – ash 24. ET06 – etch 500 Å pad oxide 25. CL01 – pre-gate oxide RCA clean 26. ET06 – etch native oxide 27. OX06 – 30 Å gate oxide, Tube 4 28. CV01 – poly deposition, 2500 Å 29. PH03 – level 6 - poly gate 30. ET08 – poly gate plasma etch 31. ET07 – ash 32. CL01 – RCA clean 33. OX05 – poly re-ox, 250 Å, Tube 4 34. PH03 – level 7 - p-LDD 35. IM01 – 9E14, BF2, 20 KeV 36. ET07 – ash 37. PH03 – level 8 - n-LDD 38. IM01 – 5E15, P31, 20 KeV 39. ET07 – ash 40. CL01 – RCA clean 41. CV02 – nitride spacer 2500Å 42. ET39 – sidewall spacer etch 43. PH03 – level 9 - N+D/S 44. IM01 – 1E15, P31, 25 KeV 45. ET07 – ash 46. PH03 – level 10 - P+ D/S 47. IM01 – 5E15 BF2, 27 KeV 48. ET07 – ash 49. CL01 – RCA clean 50. OX08 – DS Anneal, RTP 51. ET06 – Silicide pad ox etch 52. ME03 – HF dip & Ti Sputter 53. RT01 – RTP 5 sec, 650C 54. ET11 – Unreacted Ti Etch 55. RT02 – RTP 5 sec, 700C 56. CV03 – TEOS, P-5000, 3000Å 57. PH03 – level 11 - CC 58. ET06 – CC etch 59. ET07 – ash 60. CL01 – RCA clean 61. ME01 – Aluminum 62. PH03 – level 12-metal 63. ET15 – plasma Al Etch 64. ET07 – ash 65. CV03 – TEOS 66. PH03 – Via 67. ET26 Via Etch 68. ME01 Al Deposition 69. PH03 – Metal 2 70. ET07 - Ash 72. SI01 – sinter 73. SEM1 74. TE01 75. TE02 76. TE03 77. TE04 (Revision 05-02-14) L = 0.5 m VDD = 3.0 V VTN = 0.75 V VTP = - 0.75V

FACTORY TEAMS - THURSDAY Red Grou 1. Chakrakeerthi 2. Shreyas 3. Orange Group 1. Pooja 2. Timothy 3. Yellow Group 1. Rahnuma 2. Veena 3. Green Group 1. Venkatesh 2. Muhammad 3. Blue Group 1. Ky-El 2. Arshia 3. Every two weeks groups shift discipline (to the right). For example the red group does Diffusion week 1&2, Red does Lithography week 3&4, Red does CVD/Plasma week 5&6, etc. Discipline Diffusion Lithography PVD/Plasma Etch CVD/PECVD Wet Etch/CMP Bruce Furnace AG-RTP Blue M Oven Nanospec Spectromap CDE Resistivity Map Canon Stepper SSI Track CD Linewidth Overlay Branson Asher CVC601 Drytech Quad Lam490 Lam4600 Nanospec Tencore P2 ASM 6”LPCVD P-5000 Nanospec Spectromap Varian 350D Al Wet Etch BOE Etch RCA Clean Hot Phos Nitride Etch BOE Solvent Strip CMP and CMP Clean Nanospec Surfscan SEM While in each discipline the students will Process lots requiring steps in that discipline Perform follow up Inspection and Metrology Investigate and Update SPC data Monitor non-device process metrics Perform a “pass down” at the end of (2 weeks) Track lots in and out of Mesa 1-15-2018

Rochester Institute of Technology Microelectronic Engineering Dr. Lynn Fuller Orange (Diffusion) Yellow (Lithography) Green (Plasma Etch) Blue (Implant/CVD) Red (wet Etch) Date: 4-19-18 Lot Status Report Time: 8:00 am Lot No Product Process / Version Current operation Q P STEP Next Operation Qty Comments F150903 JOHN GALT SUB-CMOS 150 ET07 X 75 SEM1 3 ORANGE F160218 ET15 2 F160922 ET26 61 BLUE F170126 ET08 40 RED F170223 GREEN F171102 IM01 21 F180118 11 OX06 F180208 6 F180322 PH03 4 ET29 YELLOW RED – Why is lot F170126 in Process?