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IC Fabrication/Process
LECTURE 5 Problem (Design Specification) Design Fab chip Patterning Process by which layers of integrated circuit are put together. Forms basis of our understanding of the design rules. Process Parameters: Capacitances, Resistances, VTO if ignored, reduced performance. Geometric Constraints: Wire size, Spacing if ignored, circuit doesn’t work! (Design rules)
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How do we transfer patterns to the surface of a silicon wafer?
Separate pattern for each layer makes a Mask for each pattern. Use photo lithography to transfer to wafer. 1. Oxidation - expose Si wafer to O2 in furnace. Si + O2 -> SiO2 Si3N4 SiO2 Si 44% Si
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2. Lithography PR SiO2 Si UV light Mask Organic solvent (developer)
Breaks down
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3. Etching etchant Dissolves SiO2 but not resist exposed resist faster
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4. Ion Implantation (I/I)
5. Diffusion
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NMOS Process sequence
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CMOS Processes Twin-Tub N-well P-well Better NMOS Better PMOS P-well
Both N-, P-MOS optimized Twin-Tub P-well EPI P-well P+ N+ N-sub Better PMOS N-well Better NMOS CMOS Processes
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N-Well CMOS Process
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MOS PROCESSING TECHNOLOGY
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Advanced CMOS Process Flow
Grow Pad Oxide. Deposit CVD Nitride Nitride Pad oxide p-type substrate RIE Shallow Trench in Silicon Photoresist Photoresist Nitride Pad oxide p-type substrate
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Shallow trench isolation
Grow Pad Oxide. Deposit Thick CVD Oxide CVD oxide Nitride p-type substrate CMP Planarization Shallow trench isolation p-type substrate
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Well Lithography and Implant (also channel doping)
p-doping n-doping STI p-type substrate STI STI n-well Grow Gate Oxide and Deposit Polysilicon Film Gate oxide polysilicon p-doping n-doping p-type substrate STI STI STI n-well
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Source-Drain Lithography and Implant
Gate Lithography PR PR Poly Poly p-doping n-doping p-type substrate STI STI STI n-well Source-Drain Lithography and Implant n+ poly p+ poly n+ n+ p+ p+ STI p-type substrate STI STI p-doping n-doping n-well
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Oxide Spacer Formation by CVD and RIE
n+ poly p+ poly n+ n+ p+ p+ p-type substrate STI STI STI p-doping n-doping n-well Self-Aligned Silicide Process Oxide spacer Silicide Silicide n+ poly p+ poly n+ n+ p+ p+ p-type substrate STI STI STI p-doping n-doping n-well
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Why CMOS is superior to NMOS? (in VLSI)
Comparison Table CMOS NMOS 1. Logic level /5V depending on ratio, poor noise margins 2. Transmission time tI tf tI > tf 3. Transmission Gate pass both logic well only pass “0”, well pass “1” will have VT drop 4. Power Dissipation zero in standby when output “0”, power dissipating 5. Precharging Scheme Both n p are available only can charge to VDD- VT for precharging bus to unless use boostrapping VDD / VSS 6. Power Supply May vary from 1.5~15V Fixed VIH/VIL, a fixed per dependent on VDD centage of VDD 7. Packing density less dense, 2N device Denser, N+1 device for N inputs for N input 8. Load/Drive ratio :1 or 2: optimize ratio 4:1 9. Layout more regular irregular
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Well Spacing and Separation Rules
NMOS PMOS Transistor Rules
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Well / substrate contacts
n-well P+ P+ P+
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