2. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 1 Rochester Institute of Technology Microelectronic Engineering ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING PMOS PROCESS DETAILS  Dr. Lynn Fuller  Motorola Professor  Microelectronic Engineering  Rochester Institute of Technology  82 Lomb Memorial Drive  Rochester, NY 14623-5604  Tel (585) 475-2035  Fax (585) 475-5041  LFFEEE@rit.edu LFFEEE@rit.edu  http://www.microe.rit.edu http://www.microe.rit.edu 3-14-2003 pmos.ppt

3. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 2 Rochester Institute of Technology Microelectronic Engineering RIT METAL GATE PMOS PROCESS  10 Micrometer Design Rules  4 Design Layers  4 Photolithography Layers  Metal Gate

4. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 3 Rochester Institute of Technology Microelectronic Engineering STARTING WAFER N-TYPE, 5 OHM-CM

5. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 4 Rochester Institute of Technology Microelectronic Engineering ID01 - IDENTIFY WAFER (SCRIBE WAFER) DE01 - FOUR POINT PROBE L950724 D1 Rhos =  /ln2 x W x V / I ohm-cm if S<<W and S<<Wafer Diameter V I S = probe spacing W = wafer thickness

6. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 5 Rochester Institute of Technology Microelectronic Engineering RCA CLEAN DI water rinse, 5 min. H 2 0 - 50 HF - 1 60 sec. HPM H 2 O–4500ml HCL-300ml H 2 O 2 – 900ml 75 °C, 10 min. SPIN/RINSE DRY APM H 2 O – 4500ml NH 4 OH–300ml H 2 O 2 – 900ml 75 °C, 10 min. DI water rinse, 5 min. DI water rinse, 5 min. PLAY ANSWER What does RCA stand for?

7. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 6 Rochester Institute of Technology Microelectronic Engineering RCA CLEAN RCA Bench Spin/Rinse/Dry Tool

8. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 7 Rochester Institute of Technology Microelectronic Engineering GROW 5000 Å OXIDE 5000 Å SiO2 Push at 900 C in N2 Ramp to 1100 C in dry O2 Start Soak at 1090 C Time = 48 min. in wet O2 Ramp down to 1000 C in N2 Pull at 1000 C in N2

9. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 8 Rochester Institute of Technology Microelectronic Engineering WET OXIDE GROWTH CHART Steam 900C 1300C 0.01 0.1 1 10 1 100 1000 Time in minutes Oxide Thickness in microns

10. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 9 Rochester Institute of Technology Microelectronic Engineering 5000 Å OXIDE GROWTH 1100°C 900 °C PushRamp-UpSoak Anneal Ramp-Down Pull 12 min20 min48 min5 min 40 min12 min 15 lmp10 lpm10 lpm15 lpm 10 lpm15 lpm N2O2O2N2 N2 N2 Interval 1 Interval 2Interval 3 Interval 4Interval 5Interval 6Interval 7 1000 °C Note: start soak at 10 °C below the soak temperature

11. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 10 Rochester Institute of Technology Microelectronic Engineering 5000 Å OXIDE GROWTH USING BRUCE FURNACE n-type substrate, 5-15 ohm-cm, (100) Bruce furnace Recipe - 250 Oxide, 5000 Å Push, 12 in/min at 800 C, 15 lmp N 2 Ramp to 1000 C, 10 lpm Dry O 2 Soak for 120 min, 10 lpm wet O 2 Plus 5 min, 15 lpm N 2 Ramp to 800 C, 10 lpm N 2 Pull, 12 in/min, 15 lpm N 2 PMOSFET PLAY

12. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 11 Rochester Institute of Technology Microelectronic Engineering OXIDE COLOR VERSUS THICKNESS TABLE SiO 2 Yes! No! Silicon To observe a valid color, the wafer must be observed perpendicular to the surface under white (all wavelengths) light or the optical path length will be different, hence the color will change with the angle.

13. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 12 Rochester Institute of Technology Microelectronic Engineering REFLECTANCE SPECTROMETER NANOSPEC FILM THICKNESS MEASUREMENT INCIDENT WHITE LIGHT, THE INTENSITY OF THE REFLECTED LIGHT IS MEASURED VS WAVELENGTH WHITE LIGHT SOURCE OPTICS WAFER MONOCHROMATOR & DETECTOR 3000 Å OXIDE 7000 Å OXIDE Oxide on Silicon400-30,000 Å Nitride400-30,000 Neg Resist500-40,000 Poly on 300-1200 Ox400-10,000 Neg Resist on Ox 300-350300-3500 Nitride on Oxide 300-3500300-3500 Thin Oxide100-500 Thin Nitride100-500 Polyimide500-10,000 Positive Resist500-40,000 Pos Resist on Ox 500-15,0004,000-30,000

14. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 13 Rochester Institute of Technology Microelectronic Engineering STEP ETCH APPARATUS BUFFERED HF Lower 1/4 inch every 45 seconds

15. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 14 Rochester Institute of Technology Microelectronic Engineering ETCH STEPS IN OXIDE ON C1 5000 Å BARE SILICON

16. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 15 Rochester Institute of Technology Microelectronic Engineering COAT WITH PHOTORESIST 5000 Å SiO2 1 µm Photoresist

17. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 16 Rochester Institute of Technology Microelectronic Engineering PHOTORESIST PROCESSING DEVELOP DI Wet CD-26 Developer 45sec. Puddle, 30sec. Rinse, 40sec., 4000rpm Spin Dry SPIN COAT Shipley812 Resist 4500rpm, 60 sec. SOFT BAKE 115 °C 60 sec. HARD BAKE 125 °C, 60 sec. RECIPE 1 for all Tracks DEHYDRATE BAKE/ HMDS PRIMING HMDS Vapor Prime 140 °C, 60 sec.

18. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 17 Rochester Institute of Technology Microelectronic Engineering SVG WAFERTRAC

19. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 18 Rochester Institute of Technology Microelectronic Engineering EXPOSE WITH LEVEL ONE DIFFUSION 0.3 seconds = 75 mj/cm2

20. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 19 Rochester Institute of Technology Microelectronic Engineering EXPOSURE, GCA 6700 G-LINE STEPPER E = It E (mj/cm2) = I(mw/cm2) t(sec)

21. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 20 Rochester Institute of Technology Microelectronic Engineering ETCH OXIDE Buffered HF 6 min. Rinse/Spin Dry

22. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 21 Rochester Institute of Technology Microelectronic Engineering ASH RESIST Asher O2 + Energy = 2 O O is reactive and will combine with plastics, wood, carbon, photoresist, etc.

23. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 22 Rochester Institute of Technology Microelectronic Engineering ASH RESIST

24. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 23 Rochester Institute of Technology Microelectronic Engineering SPIN-ON P-TYPE DOPANT Push at 900 C in N2, Ramp to 1050 C in N2, Soak for 5 min., Change from N2 to wet O2, Soak 5 min, Ramp down to 1000 C, Pull n-TYPE SILICON P-TYPE DOPANT (BORON)

25. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 24 Rochester Institute of Technology Microelectronic Engineering OXIDE ETCH and RCA CLEAN n-TYPE SILICON p-TYPE DOPANT IN SILICON

26. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 25 Rochester Institute of Technology Microelectronic Engineering MINIMUM OXIDE THICKNESS FOR DIFFUSION MASK X ox, µm 1,000 10 -1 10 - 2 10 - 3 t, Time, (min) 10 100 10 1 90 0 1200 C 1100 1000 1200 C 1100 1000 900 Boron Phos

27. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 26 Rochester Institute of Technology Microelectronic Engineering ETCH STEPS IN OXIDE ON C5 FIND SLOW AND FAST ETCH RATES 8000 Å BARE SILICON SLOW FAST

28. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 27 Rochester Institute of Technology Microelectronic Engineering PAINT RESIST STRIP ETCH C1 BARE 8000 Å BARE SILICON WITH SPIN-ON DOPANT XXXX. V/I=. FIND MINIMUM OXIDE THICKNESS TO MASK BORON DIFFUSION

29. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 28 Rochester Institute of Technology Microelectronic Engineering M N After Stain Xj = (N * M) / D (at RIT D=1.532 inch) D Groove Staining Solution - 1 Vol part HF, 2 Vol part Nitric Acid, 12 Vol part Acetic Acid After mixing drop a penny in solution for about 10 sec. result in a light blue color. Safety Stain - (does not have HF) is available from Philtec Instrument Co. Philadelphia, PA 19129-1651, (215) 848-4500, Signatone makes groove tool and wheels, (408)732-3280 M N GROOVE and STAIN C2 FIND Xj AFTER PRE DEPOSIT

30. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 29 Rochester Institute of Technology Microelectronic Engineering TRAVELING STAGE MICROSCOPE Example: If M=.003 inches and N=0.025 inches, find xj. Xj = (N * M) / D = (0.025 * 0.003)/1.588 inch) = 0.0000472 inch = 1.20 µm

31. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 30 Rochester Institute of Technology Microelectronic Engineering DE01 - FOUR POINT PROBE C1, C2, C3, C4 V I Rhos = V / I * Pi / ln 2 ohms/square = 4.53 V/ I ohms/sq p-type diffused layer FIND SHEET RESISTANCE OF DIFFUSION AFTER PREDEPOSITE

32. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 31 Rochester Institute of Technology Microelectronic Engineering FIELD OXIDE GROWTH @ 5000 A Push at 900 C in N2 Ramp to 1100 C in dry O2 Start Soak at 1090 C Time = 48 min. in wet O2 Ramp down to 1000 C in N2 Pull at 1000 C in N2 Slightly Thicker Oxide Over Diffusion

33. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 32 Rochester Institute of Technology Microelectronic Engineering PHOTOLITHOGRAPHY OXIDE

34. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 33 Rochester Institute of Technology Microelectronic Engineering 2 ND PHOTOLITHOGRAPHY ALIGNMENT VERNIERS CRITICAL DIMENSION (CD) STRUCTURES - X+ - Y+ 12 3 4 5 6 7 8 4 µm CD

35. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 34 Rochester Institute of Technology Microelectronic Engineering MEASUREMENT OF 4 µm CRITICAL DIMENSION (CD) Using an Optical microscope at 100X find the resolution target for the current photo level and set it up so that you can compare the 4 micrometer line/space pattern to the scale below. Estimate the size of the 4 micrometer line of photoresist or the size of the 4 micrometer opening in the photoresist. 5.0 4.5 4.0 3.5 3.0 2.5µm

36. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 35 Rochester Institute of Technology Microelectronic Engineering ACTIVE AREA ETCH

37. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 36 Rochester Institute of Technology Microelectronic Engineering OXIDE ETCH C3 and C4 BARE

38. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 37 Rochester Institute of Technology Microelectronic Engineering GROOVE and STAIN and 4PT PROBE C3 Xj = (N * M) / D V I 4PT PROBE D M N Groove After Stain Rhos = V / I * Pi / ln 2 ohms/square = 4.53 V/ I ohms/sq p-type diffused layer

39. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 38 Rochester Institute of Technology Microelectronic Engineering ASH RESIST, RCA CLEAN GATE OXIDE GROWTH @ 700 A 700 Å SiO2 Push at 900 C in N2 Ramp to 1100 C in dry O2 Start Soak at 1090 C Time = 25 min. in dry O2 Ramp down to 1000 C in N2 Pull at 1000 C in N2

40. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 39 Rochester Institute of Technology Microelectronic Engineering DRY OXIDE GROWTH CHART Time in minutes Oxide Thickness in microns 900C 1300C 0.01 0.1 1 10 10010 1,000 10,000 Dry O 2

41. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 40 Rochester Institute of Technology Microelectronic Engineering PHOTOLITHOGRAPHY CONTACT CUT

42. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 41 Rochester Institute of Technology Microelectronic Engineering OXIDE ETCH C4 BARE

43. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 42 Rochester Institute of Technology Microelectronic Engineering GROOVE and STAIN and 4PT PROBE C4 Xj = (N * M) / D V I 4PT PROBE D M N Groove After Stain Rhos = V / I * Pi / ln 2 ohms/square = 4.53 V/ I ohms/sq p-type diffused layer

44. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 43 Rochester Institute of Technology Microelectronic Engineering CONTACT CUT ETCH GatePhotoresist SourceDrain n-type p-type 5000 Å 700 Å

45. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 44 Rochester Institute of Technology Microelectronic Engineering ASH RESIST, RCA CLEAN and SPUTTER ALUMINUM Aluminum

46. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 45 Rochester Institute of Technology Microelectronic Engineering METAL DEPOSITION PLAY

47. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 46 Rochester Institute of Technology Microelectronic Engineering PHOTOLITHOGRAPHY METAL

48. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 47 Rochester Institute of Technology Microelectronic Engineering ETCH ALUMINUM Aluminum Etchant: Phosphoric, Acetic, Nitric Acid 50 °C, 2 min Rinse in DI water 5 min. Photoresist Al

49. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 48 Rochester Institute of Technology Microelectronic Engineering ALUMINUM ETCH APPARATUS ALUMINUM, ETCH Thermometer Probe with glass cover Wafer Boat Teflon Stirrer & Guide Plate Wafers Controller Hot Plate Holes Teflon Cover 50°C PLAY

50. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 49 Rochester Institute of Technology Microelectronic Engineering ASH RESIST Gate Crossunder to source Source Drain n-type p-type 5000 Å 700 Å Crossover

51. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 50 Rochester Institute of Technology Microelectronic Engineering SINTER, 425 °C, N 2 /H 2 Native Oxide Before Sinter After Sinter Reduce Surface States Reduce Contact Resistance Oxygen Hydrogen, neutral region Silicon Crystal + charge region Silicon DiOxide Interface silicon atom that lost an electron

52. © June 4, 2002 Dr. Lynn Fuller, Motorola Professor RIT Metal Gate PMOS Process Page 51 Rochester Institute of Technology Microelectronic Engineering TEST PMOS TRANSISTOR CROSSUNDER GATE SOURCE DRAIN S G D D X