1. EMT362: Microelectronic Fabrication
Ramzan Mat Ayub; SATF 2005
EMT362: Microelectronic Fabrication
CMOS WELL TECHNOLOGY
Part 2
Ramzan Mat Ayub
School of Microelectronic Engineering

2. In CMOS Technology, both n and p-channel transistor must be fabricated
Ramzan Mat Ayub; SATF 2005
In CMOS Technology, both n and p-channel transistor must be fabricated
on the same wafer.
To accommodate the device type that cannot be built on the particular
substrate, regions of a doping type opposite to the substrate must be formed.
These regions are called WELL and normally the first module to be introduced.
Excess dopants are selectively introduced to achieve a certain depth and
concentration profile.

3. TYPE OF WELLS P Well N-Well Twin-Well On P OR N-type Substrate
Ramzan Mat Ayub; SATF 2005
TYPE OF WELLS
P Well
N-Well
Twin-Well On P OR N-type Substrate
Retrograde Well

4. Ramzan Mat Ayub; SATF 2005
P – WELL CMOS
The p-well process, involves the creation of p-regions in n-type substrate for
the fabrication of n-channel transistor.
The p-wells are formed by implanting a p-type dopant into an n-substrate.
The n-substrate doping level normally between 3 x 1014 to 1 x 1015, and p-well
doping concentration normally done at 5 to 10 times higher.

5. Doping concentration 1014 to 1 x 1015
Ramzan Mat Ayub; SATF 2005
Basic P – WELL Process Step
n-substrate,
Doping concentration 1014 to 1 x 1015
Resistivity 1-50 Ohm-cm
Step 1
Wafer Cleaning- clean wafer surface from particles, organic,
inorganic and metallic contaminants.

6. Doping concentration 1014 to 1 x 1015
Ramzan Mat Ayub; SATF 2005
n-substrate,
Doping concentration 1014 to 1 x 1015
Resistivity 1-50 Ohm-cm
Step 2
Pad Oxidation – to grow thin thermal oxide ( A) to prevent
Crystal damage during ion implantation. Normally done using
wet oxidation 900 to 980C.

7. Doping concentration 1014 to 1 x 1015
Ramzan Mat Ayub; SATF 2005
n-substrate,
Doping concentration 1014 to 1 x 1015
Resistivity 1-50 Ohm-cm
Step 3
Photoresist coating

8. Doping concentration 1014 to 1 x 1015
Ramzan Mat Ayub; SATF 2005
UV light
Mask
n-substrate,
Doping concentration 1014 to 1 x 1015
Resistivity 1-50 Ohm-cm
Step 4
Exposure

9. Doping concentration 1014 to 1 x 1015
Ramzan Mat Ayub; SATF 2005
n-substrate,
Doping concentration 1014 to 1 x 1015
Resistivity 1-50 Ohm-cm
Step 5
PR Development

10. Doping concentration 1014 to 1 x 1015
Ramzan Mat Ayub; SATF 2005
n-substrate,
Doping concentration 1014 to 1 x 1015
Resistivity 1-50 Ohm-cm
Step 6 – P-type dopant ion implantation, Boron (5 to 10 times higher
concentration to the substrate, KeV implantation energy.

11. Doping concentration 1014 to 1 x 1015
Ramzan Mat Ayub; SATF 2005
n-substrate,
Doping concentration 1014 to 1 x 1015
Resistivity 1-50 Ohm-cm
Step 7 – PR Strip, plasma followed by wet

12. Doping concentration 1014 to 1 x 1015
Ramzan Mat Ayub; SATF 2005 Xj
n-substrate,
Doping concentration 1014 to 1 x 1015
Resistivity 1-50 Ohm-cm
Step 8 – Drive-in, to drive well into the desired junction depth.
Diffusion 1000C in N2.

13. Doping concentration 1014 to 1 x 1015
Ramzan Mat Ayub; SATF 2005 Xj
n-substrate,
Doping concentration 1014 to 1 x 1015
Resistivity 1-50 Ohm-cm
Step 9 – Oxide etch.

14. Doping concentration 1014 to 1 x 1015
Ramzan Mat Ayub; SATF 2005 Xj
n-substrate,
Doping concentration 1014 to 1 x 1015
Resistivity 1-50 Ohm-cm
Step 10 – Sacrificial oxide grow, normally the same thickness as
pad oxide.

15. Doping concentration 1014 to 1 x 1015
Ramzan Mat Ayub; SATF 2005 Xj
n-substrate,
Doping concentration 1014 to 1 x 1015
Resistivity 1-50 Ohm-cm
Step 11 – Sacrificial oxide removal, wet etch.

16. After front-end process, p-well CMOS technology.
Ramzan Mat Ayub; SATF 2005
PMOS
NMOS p+ p+ n+ n+
p-well
n-substrate
After front-end process, p-well CMOS technology.

17. The 1st CMOS technology, commercially introduced in early 60s.
Ramzan Mat Ayub; SATF 2005
The 1st CMOS technology, commercially introduced in early 60s.
Advantages over n-well CMOS
balanced performance for both NMOS and PMOS (good for pure logic product)
suit better for application required isolated p-region (n-channel FET for analog)
less susceptible to field inversion problem (p-well can be used as a channel stop)
better for SRAM product (soft error rate factor)
Disadvantages over n-well CMOS
NMOS performance degradation
harder to handle substrate current from well, since NMOS produce more hot carriers

18. Ramzan Mat Ayub; SATF 2005
N – WELL CMOS
The n-well process, involves the creation of n-regions in p-type substrate for
the fabrication of p-channel transistor.
The n-wells are formed by implanting a n-type dopant into an n-substrate.
The p-substrate doping level normally between 3 x 1014 to 1 x 1015, and n-well
doping concentration normally done at 5 to 10 times higher.

19. Basic N – WELL Process Step
Ramzan Mat Ayub; SATF 2005
Basic N – WELL Process Step
Identical to the formation of P-Well CMOS
Tutorial 1, Q2
PMOS
NMOS p+ p+ n+ n+
n-well
p-substrate
After front-end process, n-well CMOS technology.

20. Advantages over p-well CMOS
Ramzan Mat Ayub; SATF 2005
Advantages over p-well CMOS
Performs better in high speed, high density applications (majority of EPROM, DRAM
and MicroP in 1.25 to 2um process technology were implemented using n-well CMOS).
Disadvantages over p-well CMOS
Sensitive to field inversion, need an additional channel stop process

21. N-well depth needed to avoid vertical puncthrough to the substrate?
Ramzan Mat Ayub; SATF 2005
Example
An n-well CMOS process is to be developed for operation with power supply
voltage of VDD=5V. The substrate doping of the p-type wafer is 1 x 1015 atoms / cm3.
The n-wells are to have an average doping concentration of 1 x 1016 atoms/cm3.
The p-channel MOSFET sources and drains are to have junction depths of 0.4um
and and average dopant density of 1 x 1018 atoms/cm3. What is the minimum
N-well depth needed to avoid vertical puncthrough to the substrate?

22. Tutorial 1, Q3 SOLUTION PMOS NMOS
Ramzan Mat Ayub; SATF 2005
SOLUTION
PMOS
NMOS
1 x 1018 p+ p+ n+
0.4um n+ ??
1 x 1016
n-well
1 x 1015
p-substrate
Verticle puncthrough will occur if the depletion regionof the source/drain to well-junction
were to contact the depletion region of the well-substrate junction when VDD=5V.
Calculate the V0 for both diodes
Calculate W withour external bias for both diodes.
Tutorial 1, Q3

23. Ramzan Mat Ayub; SATF 2005
TWIN–WELL CMOS
Two separate wells are formed for n and p-channel transistors on a lightly
doped substrate.
The substrate maybe either a lightly doped n or p-type material, or a thin,
lightly doped epitaxial layer.
Each of the wells dopants is implanted separately and then driven to the
desired depth.

24. Basic TWIN – WELL Process Step
Ramzan Mat Ayub; SATF 2005
Basic TWIN – WELL Process Step
n or p or epi-substrate,
Step 1
Wafer Cleaning- clean wafer surface from particles, organic,
inorganic and metallic contaminants.

25. Pad Oxidation – to grow thin thermal oxide (200-500A) to prevent
Ramzan Mat Ayub; SATF 2005
Step 2
Pad Oxidation – to grow thin thermal oxide ( A) to prevent
Crystal damage during ion implantation. Normally done using
wet oxidation 900 to 980C.

26. Silicon nitride deposition – masking for p-channel area. Normally
Ramzan Mat Ayub; SATF 2005
Step 3
Silicon nitride deposition – masking for p-channel area. Normally
done using LPCVD or PECVD process. Typical thickness between
1500 – 2000A.

27. Ramzan Mat Ayub; SATF 2005
Step 4
Photoresist coating

28. Ramzan Mat Ayub; SATF 2005
UV light
Mask
Step 5
Exposure

29. Ramzan Mat Ayub; SATF 2005
Step 6
PR Development

30. Nitride Etch- RIE process, stop at oxide
Ramzan Mat Ayub; SATF 2005
Step 7
Nitride Etch- RIE process, stop at oxide

31. Step 8 – P-type dopant ion implantation for P-well, Boron (5 to 10
Ramzan Mat Ayub; SATF 2005
Step 8 – P-type dopant ion implantation for P-well, Boron (5 to 10
times higher concentration to the substrate, KeV implantation
energy.

32. Step 9 – PR Strip, plasma followed by wet
Ramzan Mat Ayub; SATF 2005
Step 9 – PR Strip, plasma followed by wet

33. Step 10 – Sacrificial LOCOS oxidation
Ramzan Mat Ayub; SATF 2005
Step 10 – Sacrificial LOCOS oxidation

34. Ramzan Mat Ayub; SATF 2005
Step 11 – Etch Nitride

35. Step 12 – Implant N-well, Phosphorus, 100-150 KeV
Ramzan Mat Ayub; SATF 2005
Step 12 – Implant N-well, Phosphorus, KeV

36. Ramzan Mat Ayub; SATF 2005
Step 13 – Drive-in

37. Ramzan Mat Ayub; SATF 2005
Step 14 – Oxide etch

38. Step 15 – Sacrificial Oxide
Ramzan Mat Ayub; SATF 2005
Step 15 – Sacrificial Oxide

39. Step 16 – Sacrificial removal
Ramzan Mat Ayub; SATF 2005
Step 16 – Sacrificial removal

40. After front-end process, Twin-well CMOS technology.
Ramzan Mat Ayub; SATF 2005
PMOS
NMOS p+ p+ n+ n+
n-well
p-well
n or p-substrate
After front-end process, Twin-well CMOS technology.

41. The most widely used well scheme in sub-micron CMOS technology
Ramzan Mat Ayub; SATF 2005
The most widely used well scheme in sub-micron CMOS technology
Advantages
Doping profile for each device can be set independently.
Compatibility with advanced isolation structure (trench and SEG), allow closer
n+ to p+ spacing design rules i.e denser circuit.
substrate can be changed without changing the process flow
enable the implementation of self aligned channel stop.

42. Lateral Diffusion in Conventional Wells
Ramzan Mat Ayub; SATF 2005
Lateral Diffusion in Conventional Wells
Lateral diffusion of dopants
Lateral diffusion limits circuit density in conventional wells
Approximate lateral diffusion; 0.7x the junction depth
How to reduce the lateral diffusion?

43. Ramzan Mat Ayub; SATF 2005
Retrograde Well
Use high energy implant, followed by short annealing step. Well formed by
this technique is called Retrograde Well
Temperature cycle of subsequent process is tightly controlled.

44. Basic Retrograde Well Process Step
Ramzan Mat Ayub; SATF 2005
Basic Retrograde Well Process Step
n or p or epi-substrate,
Step 1
Wafer Cleaning- clean wafer surface from particles, organic,
inorganic and metallic contaminants.

45. Pad Oxidation – to grow thin thermal oxide (200-500A) to prevent
Ramzan Mat Ayub; SATF 2005
Step 2
Pad Oxidation – to grow thin thermal oxide ( A) to prevent
Crystal damage during ion implantation. Normally done using
wet oxidation 900 to 980C.

46. Silicon nitride deposition – masking for p-channel area. Normally
Ramzan Mat Ayub; SATF 2005
Step 3
Silicon nitride deposition – masking for p-channel area. Normally
done using LPCVD or PECVD process. Typical thickness between
1500 – 2000A.

47. Ramzan Mat Ayub; SATF 2005
Step 4
PR Coating

48. Ramzan Mat Ayub; SATF 2005
UV light
Step 5 – Mask 1 (Active)
Exposure

49. Ramzan Mat Ayub; SATF 2005
Step 6
PR development

50. Ramzan Mat Ayub; SATF 2005
Step 7
Nitride Etch

51. Ramzan Mat Ayub; SATF 2005
Step 8
PR strip

52. Fully recessed LOCOS oxidation
Ramzan Mat Ayub; SATF 2005
Step 9
Fully recessed LOCOS oxidation

53. Ramzan Mat Ayub; SATF 2005
Step 10
Nitride / Oxide Etch

54. Sacrificial Oxidation
Ramzan Mat Ayub; SATF 2005
Step 11
Sacrificial Oxidation

55. Ramzan Mat Ayub; SATF 2005
Step 12
PR coating

56. Ramzan Mat Ayub; SATF 2005
UV light
Step 13 – Mask 2 (P-well)
Exposure

57. Ramzan Mat Ayub; SATF 2005
Step 14
PR Development

58. Pwell Implant, Boron 180 KeV Field Implant, Boron 100KeV
Ramzan Mat Ayub; SATF 2005
P-well
Step 15
Pwell Implant, Boron 180 KeV
Field Implant, Boron 100KeV
Vt adjust implant

59. Ramzan Mat Ayub; SATF 2005
P-well
Step 16
Resist strip

60. Ramzan Mat Ayub; SATF 2005
P-well
Step 17
Resist coating

61. Ramzan Mat Ayub; SATF 2005
UV light
P-well
Step 18
Exposure

62. Ramzan Mat Ayub; SATF 2005
P-well
Step 19
PR development

63. Nwell implantation, Phosphorus 500KeV PMOS Vt adjust
Ramzan Mat Ayub; SATF 2005
n-well
p-well
Step 20
Nwell implantation, Phosphorus 500KeV
PMOS Vt adjust
Field Implant, Phosphorus 230 KeV

64. Ramzan Mat Ayub; SATF 2005
n-well
p-well
Step 21
PR strip

65. Dopant annealing (activation), 30 min furnace
Ramzan Mat Ayub; SATF 2005
n-well
p-well
Step 22
Dopant annealing (activation), 30 min furnace

66. After front-end process, Retrograde Well CMOS technology.
Ramzan Mat Ayub; SATF 2005
PMOS
NMOS p+ p+ n+ n+
n-well
p-well
After front-end process, Retrograde Well CMOS technology.

67. High packing density (smaller n+ to p+ rules)
Ramzan Mat Ayub; SATF 2005
The most widely used well scheme in deep sub-micron CMOS technology (<0.35um)
Advantages
High packing density (smaller n+ to p+ rules)
Lower leakage current (punchthrough susceptibility improved)
Lateral diffusion of Boron is eliminated, reduce Boron encroachment into active
Higher field device threshold voltage due to less Boron segregation into oxide.
PMOS
NMOS p+ p+ n+ n+
punchthrough
Boron encroachment
n-well
p-well
Boron segregation

68. NWELL PWELL L W POLY n+ n+ p+ p+ n+ n+ p+ p+ n+ n+ p+ p+ n+ n+ p+ p+
Ramzan Mat Ayub; SATF 2005
PWELL
NWELL n+ n+ p+ p+ L n+ n+ p+ p+ W n+ n+ p+ p+ n+ n+ p+ p+
POLY

69. Field Device - METAL CARRYING 5V WELL CONC n+ n+ n+ n+
Ramzan Mat Ayub; SATF 2005
METAL CARRYING 5V
WELL CONC n+ n+
FOX
FOX n+ n+
FOX
P-Well
P-Well
Field Device -

70. MTC DESIGN RULES (REROGRADE WELL)
Ramzan Mat Ayub; SATF 2005
MTC DESIGN RULES (REROGRADE WELL) No
Description
0.35um Target
0.5um Target
Width
Space
Pitch 1
N+ / PW to P+/NW
2.40
3.00
ISSI DESIGN RULES
(TWIN-WELL)
N+ to P+ > = 7.40 um

71. RETROGRADE WELL CONVENTIONAL WELL LOG N SILICON DEPTH
Ramzan Mat Ayub; SATF 2005
RETROGRADE WELL
CONVENTIONAL WELL
LOG N
SILICON DEPTH

72. Ramzan Mat Ayub; SATF 2005
Conclusion
IN CHOOSING THE RIGHT WELL PROFILES, FACTORS TO BE CONSIDERED ARE;
CIRCUIT PERFORMANCE PARAMETERS (VT, BV, LEAKAGE CURRENT)
LAY-OUT DENSITY
FABRICATION COST
LATCH-UP SUSCEPTIBILITY
PERFORMANCE WISE;
MAXIMIZE DRIVE CURRENT
MINIMIZE JUNCTION CAPACITANCE AND BODY EFFECT
DENSITY WISE (TO PUT N & P-CHANNEL TRANSISTOR CLOSER) – RECALL D.RULES
SUPRESS PUNCHTHROUGH
HIGH FIELD THRESHOLD VOLTAGE }
LOWER
CONCENTRATION }
HIGHER
CONCENTRATION