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SOFI R EVIEW M EETING - C ONFIDENTIAL 1 CONFIDENTIAL SOFI : WP3 - Silicon Chips SOFI meeting – 20 January 2012 - Rome.

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Presentation on theme: "SOFI R EVIEW M EETING - C ONFIDENTIAL 1 CONFIDENTIAL SOFI : WP3 - Silicon Chips SOFI meeting – 20 January 2012 - Rome."— Presentation transcript:

1 SOFI R EVIEW M EETING - C ONFIDENTIAL 1 CONFIDENTIAL SOFI : WP3 - Silicon Chips SOFI meeting – 20 January 2012 - Rome

2 SOFI R EVIEW M EETING - C ONFIDENTIAL 2 WP3 – Silicon Chips RF electrode design (UKA/SELEX/IMEC) RF electrode design (UKA/SELEX/IMEC) Optical Design (UKA/IMEC) Optical Design (UKA/IMEC) Low loss slot waveguides (IMEC/UKA) Low loss slot waveguides (IMEC/UKA) Cladding opening (IMEC) Cladding opening (IMEC) Metallization (IMEC) Metallization (IMEC) Doping (IMEC) Doping (IMEC)

3 SOFI R EVIEW M EETING - C ONFIDENTIAL 3 General Process flow Passive waveguides (advanced passives process) Implantations (multiple levels + activation) Silicidation (litho, etch, deposition, anneal, etch) Top oxide with planarization (CMP) Contacts (litho, etch, filling, CMP) Metal 1 Passivation Waveguide exposure (dry + wet etch) WW Cu buried oxide silicon BEOL oxide (p-)doped(n-)dopedsilicide Al electro-optic cladding

4 SOFI R EVIEW M EETING - C ONFIDENTIAL 4 Workpackage 3 Task 3.1: Photonic Design Task 3.2: Waveguide process optimization Task 3.3: Doping process Task 3.4: Contacting process Task 3.5: Electrical design Task 3.6: Waveguide exposure Task 3.7: Device fabrication

5 SOFI R EVIEW M EETING - C ONFIDENTIAL 5 OPTICAL DESIGN UKA - IMEC

6 SOFI R EVIEW M EETING - C ONFIDENTIAL 6 Mask designs SOFI1 (SiPP03 maskset) -advanced passives + implants -metallization in Ghent -silicon fabrication finished - metallization SOFI2 (SiPP09 maskset) -advanced passives + implants -CMOS compatible metallization (Leuven) -in fabrication SOFI2.5 (SiPP15 mask set) -test structures for V-grooves -tests for MMI and basic building blocks -tests for Optical fourier transform (filters, AWGs…) -slot waveguides -MZI “modulators” for chalcogenide -Resonant structures for 2.4

7 SOFI R EVIEW M EETING - C ONFIDENTIAL 7 SiPP03 process layers Advanced Passives (efficient grating couplers, 2 layers) Standard Passives (waveguides, sockets, 2 layers) Implants (2 layers) Silicide (1 layer ) Waveguide clearance (1 layer) Metallization (1 layer) Polymer opening (1 layer) Leuven (200mm) Ghent (samples)

8 SOFI R EVIEW M EETING - C ONFIDENTIAL 8 SiPP09 SOFI Loss structures carrier modulators electrical test structures

9 SOFI R EVIEW M EETING - C ONFIDENTIAL 9 SiPP09 – after maskprep markers and metrology

10 SOFI R EVIEW M EETING - C ONFIDENTIAL 10 Dummies and tiling Dummies on the passives control etch rate (etch rate loading) CMP stop in advanced passives Tiling on metal 1 Control etch rate Control CMP tiles outside M1 regions perforation inside large M1 regions

11 SOFI R EVIEW M EETING - C ONFIDENTIAL 11 SLOT WAVEGUIDES IMEC - UKA

12 SOFI R EVIEW M EETING - C ONFIDENTIAL 12 Low loss slot waveguides Requirement: smooth-sidewall, 100nm wide slots : 5dB/cm Difficult: On the limits for 193nm dry lithography Needs to print on 150nm topography (close by) Needs sufficiently thick resist to etch 220nm buried oxide silicon 150nm 100nm

13 SOFI R EVIEW M EETING - C ONFIDENTIAL 13 3.2 Slot waveguide process High quality slot waveguides Approach 0: Direct patterning Approach 1: two-step transfer: Failed Approach 2: Lithographic optimization Dual exposure litho (SLOT + WG) + too complex Phase shift mask (PSM): used for SOFI 1 Dual exposure with PSM Approach 3: Separate litho layer + separate etch Backup: Optimize transfer process Approach 4: Hard mask instead of resist mask (STI): works Approach 5: Spacer-based (used for transistor gates)

14 SOFI R EVIEW M EETING - C ONFIDENTIAL 14 SOFI1 process flow for slot/socket pattering Starting substrate SiN hard mask depo BARC + Photoresist coat 193 nm photo HM open 220nm poly etch PR stripped during etch 150 nm 220 nm SiO2 Si SiN removal

15 SOFI R EVIEW M EETING - C ONFIDENTIAL 15 Results (SEM images Dietmar) PSM: sidelobe patterns incomplete etch design error

16 SOFI R EVIEW M EETING - C ONFIDENTIAL 16 Process for SOFI2: WGSLOT first (see separate slide set) Oxide/nitride hard mask deposition Lithography Etch BARC etch Hard-mask etch In-situ resist strip Silicon etch Hard mask strip (hot phosphoric acid)

17 SOFI R EVIEW M EETING - C ONFIDENTIAL 17 SOFI2 etch

18 SOFI R EVIEW M EETING - C ONFIDENTIAL 18 Slot and WG width 18

19 SOFI R EVIEW M EETING - C ONFIDENTIAL 19 IMPLANTS CARRIER MODULATORS IMEC

20 SOFI R EVIEW M EETING - C ONFIDENTIAL 20 3.3 Dopant Implantations Implantation Variables: Dose, Energy, Angle Default Mask: 248nm litho mask (overlay alignment 150nm) Silicidation Create a Si/Ni allow for an ohmic contact with metal electrodes buried oxide silicon doped silicide

21 SOFI R EVIEW M EETING - C ONFIDENTIAL 21 Implanted device tests Carrier dispersion modulators (running development in imec) Similar geometry as SiPP03 devices Various pn and pin waveguide geometries Doping test structures Status Very nice results state-of-the art modulation efficiency and device performance 0.7 V.cm (interdigitated p-n junction) 12 Gbps MZI operation with lumped electrodes 40Gbps operation with TW electrodes (measurements in KIT) 0.5 Vpp operation (9dB ER, 10G) in ring modulator

22 SOFI R EVIEW M EETING - C ONFIDENTIAL 22 Eye diagrams with the lumped electrode at different bit rates 11.02 dB @4 Gbit/s 9.73 dB @8 Gbit/s 9.26 dB @10 Gbit/s 4.9 dB @12 Gbit/s

23 SOFI R EVIEW M EETING - C ONFIDENTIAL 23 Travelling wave electrode for 40 Gbit/s modulation Coplanar waveguide is carefully designed to achieve: 50 Ω impedance ； low RF propagation loss; Velocity match with optical signal. 25 Gbit/s28 Gbit/s 35 Gbit/s 40 Gbit/s For the travelling wave electrode, RF signal is boosted to 8 Vpp by an amplifier.

24 SOFI R EVIEW M EETING - C ONFIDENTIAL 24 METALLIZATION IMEC

25 SOFI R EVIEW M EETING - C ONFIDENTIAL 25 Generation 1 (SiPP03) buried oxide Undoped Wire or Slot waveguide silicide electro-optic cladding silicide p-doped Optional: Au or Al ~1um buried oxide p-dopedsilicide Optional: Au or Al

26 SOFI R EVIEW M EETING - C ONFIDENTIAL 26 resist Post processing 1 (Ghent) resist remove silicide blok layer Mask layer: PROCESS_CONT_4

27 SOFI R EVIEW M EETING - C ONFIDENTIAL 27 Oxide strip Before HF After HF unprotected silicide

28 SOFI R EVIEW M EETING - C ONFIDENTIAL 28 resist Post processing 2 (Ghent) metallization Mask layer: PROCESS_CONT_3 resist

29 SOFI R EVIEW M EETING - C ONFIDENTIAL 29 Post processing 3 (RB/UKA/GO) polymer deposition

30 SOFI R EVIEW M EETING - C ONFIDENTIAL 30 resist Post processing 4 (Ghent) resist Mask layer: PROCESS_CONT_3 polymer opening Solvent should not attack purple polymer Leave resist on?

31 SOFI R EVIEW M EETING - C ONFIDENTIAL 31 Generation 2 (SiPP09) WW Cu buried oxide BEOL oxide undoped silicide Al electro-optic cladding silicide p-doped WW Cu buried oxide BEOL oxide p-dopedsilicide Al electro-optic cladding

32 SOFI R EVIEW M EETING - C ONFIDENTIAL 32 Contact holes for SOFI2

33 SOFI R EVIEW M EETING - C ONFIDENTIAL 33 Problem: high waveguide losses Loss, measured on full device wafers Passive ~3-5dB/cm Silicided: similar After M1 (+ SiC passivation and sintering): 20dB/cm After full passivation: 50dB/cm all device lots which have been metallized Cause: unknown (under investigation)

34 SOFI R EVIEW M EETING - C ONFIDENTIAL 34 RF DESIGN UKA – SELEX - IMEC

35 SOFI R EVIEW M EETING - C ONFIDENTIAL 35 RF design of SOFI 2 Input needed from KIT and SELEX for D3.3.

36 SOFI R EVIEW M EETING - C ONFIDENTIAL 36 CLADDING OPENING IMEC

37 SOFI R EVIEW M EETING - C ONFIDENTIAL 37 Back-end opening Required for polymer integration Selective stop layer on waveguide: SiC, AlOx,... Questions: Is it needed? (or is timed etch OK?) optical quality (index, losses, passivation) wet etch or dry etch? Selective etch test planned on back-end of carrier dispersion modulators Development lot in preparation

38 SOFI R EVIEW M EETING - C ONFIDENTIAL 38 DEVICE FABRICATION IMEC

39 SOFI R EVIEW M EETING - C ONFIDENTIAL 39 Status First generation devices : SiPP03 mask. Device lot out of the pilot line Unmetallized Samples shipped Metallization ongoing Second generation devices: SiPP09 mask. Wafers in fabrication (FC etch) Expected devices: Q1/Q2 2012

40 SOFI R EVIEW M EETING - C ONFIDENTIAL 40 Summary RF electrode design Electrodes designed for generation 1 and 2 Waiting for feedback of fabrication Electrodes designed for generation 1 and 2 Waiting for feedback of fabrication Optical design SOFI 2 mask - SOFI modulators SOFI 2.5 mask - passives Next: SOFI 3 SOFI 2 mask - SOFI modulators SOFI 2.5 mask - passives Next: SOFI 3 Slot patterning 100nm slot Hard-mask based process Seems to work. waiting for loss measurement 100nm slot Hard-mask based process Seems to work. waiting for loss measurement Cladding opening Development setting up Etch experiments without stop layer Development setting up Etch experiments without stop layer Metal Contacting W Cu silicide Al Tungsten contacts Copper Heaters Aluminium Passivation Device lot out High losses! Tungsten contacts Copper Heaters Aluminium Passivation Device lot out High losses! Dopant Implantation N++ N P P++ High and low doses Control of profile Test: pn modulators Very good modulator performance High and low doses Control of profile Test: pn modulators Very good modulator performance

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