1. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-1  10 Micrometer Design Rules  4 Design Layers  4 Photolithography Layers  Metal (Aluminum) Gate Metal Gate PMOS Process This is the process flow you will use to fabricate your own transistors in the sophomore level EMCR350 course

2. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-2 Process Flows Resistors Get wafer, scribe and clean Grow masking oxide Pattern for diffusion Etch masking oxide Strip resist Clean and spin on dopant Diffuse Strip off dopant source and masking oxide Grow new thick oxide Pattern for contact cuts Etch thick oxide Strip resist Deposit Aluminum Pattern for aluminum etch Etch Aluminum Strip resist Sinter PMOS Transistors Get wafer, scribe and clean Grow masking oxide Pattern for diffusion Etch masking oxide Strip resist Clean and spin on dopant Diffuse Strip off dopant source and masking oxide Grow new thick oxide Pattern for thin (gate) oxide Grow gate oxide Pattern for contact cuts Etch thick oxide Strip resist Deposit Aluminum Pattern for aluminum etch Etch Aluminum Strip resist Sinter 1 1 2 3 4 2 3

3. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-3 Design Rules  The smallest a contact can be is one unit (lambda, ) by one unit.  In this case lambda will be 10 microns  Diffusion and metal have to extend at least one unit around a contact  The gate oxide has to extend over a diffusion by at least on unit

4. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-4 STARTING WAFER N-TYPE, 5 OHM-CM Silicon

5. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-5 ID01 - Scribe Identification Code on the Wafer DE01 - Four Point Probe to Check Resistivity L030924 D1 V I

6. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-6 OXIDE THICKNESS COLOR CHART

7. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-7 Dry Oxidation 800C (100) Si (111) Si 900C 1000C 1200C 1100C 800C 900C 1000C 1100C 1200C 0.1 1.010.0 0.1 1.0 10.0 Oxide Thickness (  m) 0.1 1.0 0.01 Oxidation time in hours

8. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-8 Steam Oxidation (111) Si 850C 900C 1000C 1100C 1200C 0.1 1.0 10.0 Oxide Thickness (  m) 0.1 10 0.01 1 Oxide Thickness (  m) 0.1 10 0.01 1 0.1 1.0 10.0 Oxidation time in hours (100) Si 950C 1050C 1150C 850C 900C 1100C 1200C 950C 1050C 1150C 1000C

9. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-9 MINIMUM OXIDE THICKNESS FOR DIFFUSION MASKING X ox, µm 1,000 10 -1 10 -2 10 -3 t, Time, (min) 10 100 10 1 900 1200 1100 1000 Boron Phos. 900 1200 C 1100 1000

10. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-10 RCA Clean then Grow 5000 Å Oxide 5000 Å SiO 2 Push at 900 C in N 2 Ramp to 1100 C in dry O 2 Start Soak at 1090 C Time = 48 min. in wet O 2 Ramp down to 1000 C in N 2 Pull at 1000 C in N 2 Bare silicon After silicon dioxide growth (should look blue-green) It can be hard to tell under the microscope

11. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-11 BUFFERED HF STEP ETCH APPARATUS Lower 1/4 inch every 30 seconds Oxide Plastic, right!

12. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-12 ETCH STEPS IN OXIDE ON C1 BARE SILICON 700 Å 1400 Å 2100 Å 2800 Å 3500 Å 4200 Å Side View Top View Actual colors are not this saturated

13. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-13 COAT WITH PHOTORESIST 5000 Å SiO 2 1 µm Positive Photoresist

14. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-14 Expose with Mask Layer One – Diffusion Openings Silicon SiO 2 opaque clear 1x Mask exposed areas develop away positive photoresist Shadow Ultra-Violet Radiation

15. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-15 ETCH OXIDE Not drawn to the same scale horizontally as vertically, the actual Cross-sectional view should be 20-50 times wider.

16. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-16 STRIP RESIST and RCA CLEAN

17. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-17 After Patterning of Diffusion Masking Oxide Bare Silicon Silicon Dioxide Diffusion openings (Bare Silicon)

18. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-18 SPIN-ON P-TYPE DOPANT

19. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-19 PRE-DEPOSIT, OXIDE ETCH and RCA CLEAN X j1  s1

20. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-20 ETCH STEPS IN OXIDE ON C5 FIND SLOW AND FAST ETCH RATES 8000 Å BARE SILICON FAST SiO 2 Mask Si Before Diffusion SLOW After diffusion and step etch

21. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-21 PAINT RESIST STRIP ETCH C1 BARE FIND MINIMUM OXIDE THICKNESS TO MASK BORON DIFFUSION 8000 Å BARE SILICON WITH SPIN-ON DOPANT XXXX. V/I=.

22. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-22 GROOVE and STAIN C2, FIND X j1 AFTER PRE-DEPOSIT X j = (N * M) / D D M N Groove After Stain

23. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-23 DE01 - FOUR POINT PROBE C1, C2, C3, C4 FIND SHEET RESISTANCE OF DIFFUSION AFTER PREDEPOSIT V I ohms/square

24. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-24 FIELD OXIDE GROWTH (5000 Å) Push at 900 C in N 2 Ramp to 1100 C in dry O 2 Start Soak at 1090 C Time = 48 min. in wet O 2 Ramp down to 1000 C in N 2 Pull at 1000 C in N 2 Slightly Thicker Oxide Over Diffusion

25. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-25 After Field (Thick) Oxide Growth Oxide over lightly doped silicon Oxide over heavily doped silicon

26. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-26 Photolithography, Mask Level 2 (define thin OXIDE regions) opaque clear Shadow Ultra-Violet Radiation

27. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-27 Active (thin oxide) Area Etch and resist strip

28. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-28 After Patterning/Etching Masking SiO 2 (before Thin Gate SiO 2 Growth)  Note that text has been added to the design to label devices, pads etc.

29. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-29 OXIDE ETCH C3 and C4 BARE These wafers are used to find the intermediate junction depths and sheet resistances as we go through the process. Note that Xj2 is deeper than Xj1. X j2  s2

30. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-30 GROOVE and STAIN and 4PT PROBE C3 ohms/square X j = (N * M) / D D M N Groove After Stain V I

31. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-31 ASH RESIST, CLEAN, GROW GATE OXIDE - 700 Å 700 Å SiO 2 Push at 900 C in N 2 Ramp to 1100 C in dry O 2 Start Soak at 1090 C Time = 50 min. in dry O 2 Ramp down to 1000 C in N 2 Pull at 1000 C in N 2 SiO 2

32. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-32 After Thin Gate Oxide Growth (dark brown areas)

33. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-33 Shadow PHOTOLITHOGRAPHY MASK LEVEL 3 - CONTACT CUT opaque clear SiO 2

34. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-34 OXIDE ETCH C4 BARE X j3  s3 Xj3 is deeper than Xj2!

35. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-35 GROOVE and STAIN and 4PT PROBE C4 ohms/square X j = (N * M) / D D M N Groove After Stain V I

36. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-36 CONTACT CUT ETCH SiO 2

37. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-37 Photomicrograph after contact cut etch and resist strip Contact Thin Oxide ~700 Å Thick Oxide

38. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-38 ASH RESIST, RCA CLEAN and SPUTTER ALUMINUM X al  s aluminum SiO 2

39. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-39 After Aluminum Deposition  Note how reflective the aluminum is Aluminum everywhere, Everything short circuited

40. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-40 PHOTOLITHOGRAPHY LEVEL 4 - METAL opaque clear v Shadow SiO 2

41. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-41 ETCH ALUMINUM (40°C Phosphoric Acid) Silicon SiO 2 Aluminum P-type photoresist

42. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-42 ASH RESIST

43. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-43 After Aluminum Etch and Resist Strip  Electrical Probe Pads are now visible, pad numbers were done in the diffusion layer

44. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-44 SINTER – Improves Contacts and Threshold Voltage Native Oxide Before Sinter After Sinter Reduce Surface States Reduce Contact Resistance Oxygen Hydrogen, neutral region Silicon Crystal + charge region SiO 2 Interface silicon atom that has Nothing to bond to (missing electron)

45. Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-45 Electrical TEST PMOS TRANSISTOR CROSS-OVER GATE SOURCE DRAIN S G D D X SiO 2 Silicon Aluminum SiO 2