1. Introduction EE1411 Manufacturing Process

2. EE1412 What is a Semiconductor? Low resistivity => “conductor” High resistivity => “insulator” Intermediate resistivity => “semiconductor” conductivity lies between that of conductors and insulators generally crystalline in structure for IC devices In recent years, however, non-crystalline semiconductors have become commercially very important polycrystallineamorphous crystalline

3. EE1413 Semiconductor Materials Galliu m (Ga) Phosphorus (P)

4. EE1414 Silicon Si has four valence electrons. Therefore, it can form covalent bonds with four of its nearest neighbors. When temperature goes up, electrons can become free to move about the Si lattice.

5. EE1415 Doping (N type) Si can be “doped” with other elements to change its electrical properties. For example, if Si is doped with phosphorus (P), each P atom can contribute a conduction electron, so that the Si lattice has more electrons than holes, i.e. it becomes “N type”: Notation: n = conduction electron concentration

6. EE1416 Doping (P type) If Si is doped with Boron (B), each B atom can contribute a hole, so that the Si lattice has more holes than electrons, i.e. it becomes “P type”: Notation: p = hole concentration

7. EE1417 CMOS Process

8. EE1418 A Modern CMOS Process Dual-Well Trench-Isolated CMOS Process

9. EE1419 Circuit Under Design

10. EE14110 Its Layout View

11. EE14111 The Manufacturing Process For a great tour through the IC manufacturing process and its different steps, check http://www.fullman.com/semiconductors/semiconductors.html

12. EE14112 Patterning of SiO2 Si-substrate (a) Silicon base material (b) After oxidation and deposition of negative photoresist (c) Stepper exposure Photoresist SiO 2 UV-light Patterned optical mask Exposed resist SiO 2 Si-substrate SiO 2 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 (e) After etching (f) Final result after removal of resist Hardened resist Chemical or plasma etch

13. EE14113 oxidation optical mask process step photoresist coatingphotoresist removal (ashing) spin, rinse, dry acid etch photoresist stepper exposure development Typical operations in a single photolithographic cycle (from [Fullman]). Photo-Lithographic Process

14. EE14114 CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers

15. EE14115 CMOS Process Walk-Through p + p-epi (a) Base material: p+ substrate with p-epi layer p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask p + p-epi SiO 2 3 SiN 4 (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer)

16. EE14116 CMOS Process Walk-Through SiO 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride (e) After n-well and V Tp adjust implants n (f) After p-well and V Tn adjust implants p

17. EE14117 CMOS Process Walk-Through (g) After polysilicon deposition and etch poly(silicon)

18. EE14118 CMOS Process Walk-Through

19. EE14119 Advanced Metallization

20. EE14120 Advanced Metallization

21. EE14121 Implantation Diffusion implantation: The wafers are placed in a quartz tube embedded in a heated furnace. A gas containing the dopant is introduced in the tube. The high temperatures of the furnace, typically 900 to 1100 °C, cause the dopants to diffuse into the exposed surface both vertically and horizontally. Ion implantation: Dopants are introduced as ions into the material. The ion implantation system directs and sweeps a beam of purified ions over the semiconductor surface. The acceleration of the ions determines how deep they will penetrate the material, while the beam current and the exposure time determine the dosage. The ion implantation method allows for an independent control of depth and dosage.

22. EE14122 Deposition Oxidation: The wafer is exposed to a mixture of high-purity oxygen and hydrogen at approximately 1000°C. The oxide is used as an insulation layer and also forms transistor gates. Chemical vapor deposition (CVD): CVD uses a gas-phase reaction with energy supplied by heat at around 850°C. silicon nitride (Si 3 N 4 ),Polysilicon, Sputtering: The aluminum is evaporated in a vacuum, with the heat for the evaporation delivered by electron-beam or ion-beam bombarding.

23. EE14123 Etching Wet etching: It uses many types of acid, base and caustic solutions to remove a material. For instance, hydrofluoric acid buffered with ammonium fluoride is typically used to etch SiO2. Dry or plasma etching: A wafer is placed into the etch tool's processing chamber and given a negative electrical charge. The chamber is heated to 100°C and brought to a vacuum level of 7.5 Pa, It then filled with a positively charged plasma (usually a mix of nitrogen, chlorine and boron trichloride). The opposing electrical charges cause the rapidly moving plasma molecules to align themselves in a vertical direction, forming a microscopic chemical and physical “sandblasting” action which removes the exposed material. It creates patterns with sharp vertical contours.