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(Chapters 29 & 30; good to refresh 20 & 21, too)
MEMS 2016 Part 1 (Chapters 29 & 30; good to refresh 20 & 21, too)
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Aspects of MEMS integration
Highly 3D Often double sided DRIE vs. KOH etching Bonding often involved Wafer 1 Wafer 2
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Double side alignment Double sided lithography requires DSP wafers
(Double Side Polished) Some alignments are critical but not all ! Often the backside structures are large, and not critically aligned to top side features.
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Alignment: diffused piezoresistors
Piezoresistors have to be positioned at the maximum defelection region OK NOT OK
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Alkaline anisotropic etchants
Etchant KOH TMAH Rate (at 80oC) 1 µm/min 0.5 Typical concentration 40% 25% Selectivity (100):(111) 200:1 30:1 Selectivity Si:SiO2 200: :1 Selectivity Si:Si3N :1 2000:1 Etch stop factor (1020cm-3)
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Membrane formation Nitride membrane; no timing needed
Timed silicon membrane; thickness depends on etch rate and wafer thickness control. Thin membrane thickness control bad. SOI wafer, membrane thickness determined by SOI device layer thickness
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Boron KOH etch stop = highly doped <Si> not etched
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Piezoresistive pressure sensor
Boron doped p++ membrane is a passive structure ! Active elements consist of the deposited polysilicon resistors.
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Thermal pressure sensor
heat sink heater resistor thermopile nitride p0 p1
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Thermal pressure sensor (2)
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Convex corner undercutting
From: Maluf
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Undercut by misorientation
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Membrane structures by top side micromachining
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Ink jet
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Ink jet (2) Process flow for ink jet: Thermal oxidation, 1 µm thick
Thermal oxidation, 1 µm thick Litho #1: chip area definition Oxide etching Boron diffusion, 2 µm deep Litho #2: chevron pattern: 1 µm width RIE of silicon, 4 µm deep Anisotropic silicon etching to undercut p++ chevrons Thermal oxidation LPCVD nitride deposition for chevron roof sealing Etchback (or polishing) of nitride LPCVD polysilicon deposition Poly doping, 20 Ohm/sq
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Ink jet (4) Litho #3: poly heater pattern Polysilicon etching
Aluminum sputtering Litho #4: metal pads Aluminum etching Passivation: CVD oxide 1 µm + PECVD nitride 0.3 µm Lithography #5: opening of bonding pads RIE of nitride and oxide Lithography #6: pattern for gold lift-off Evaporation of Cr/Au Lift of Cr/Au Lithography #7: fluidic inlet definition on the backside Anisotropic etching through the wafer from the back Resist stripping and cleaning steps omitted
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Generic surface MEMS structure
Sacrificial material Structural material Substrate material anchor
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Single mask vs. two mask cantilever
Single mask process Two mask process mask #2 mask #1 mask Etch structural layer with resist mask Etch structural layer with resist mask Etch sacrificial layer without resist Etch sacrificial layer without resist
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Material pairs & etchants
Structural film Sacrificial film Sacrificial etch(es) polysilicon oxide HF, HF vapor silicon nitride oxide HF silicon nitride Al NaOH, H3PO4 nickel Cu HCl nickel resist oxygen plasma aluminum resist oxygen plasma gold Cu HCl gold resist oxygen plasma copper resist oxygen plasma Parylene resist acetone, other solvents SU-8 Cu HCl
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Thermally excited resonator
Oxide deposition Poly deposition Lithography piezores I/I piezo doping & strip Anneal I/I Au depo Litho for heater Au heater etch & strip Poly etch & strip Oxide etch Rinse & dry poly oxide
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Surface micromachined microphone
aluminum membrane N+ diffusion oxide Give step-by-step fabrication. Estimate dimensions. Note that profiles are Microsoft profiles, not microfabrication profiles. <Si>
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Microphone (2) 0.Wafer silicon Thermal oxide 1st litho for diffusion
aluminum membrane N+ diffusion oxide 0.Wafer silicon Thermal oxide 1st litho for diffusion Etch oxide & strip resist Clean N+ diffusion Etch all oxide away CVD oxide deposition 2nd litho: oxide contact open Aluminum sputtering 3rd litho: aluminum pattern Etch aluminum & strip resist Etch oxide, rinse & dry
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Single mask SOI accelerometer
Device silicon layer DRIE Buried oxide HF wet etch Rinse & dry Benefit of SOI: Single crystal silicon, good mechanical properties Buried layer readymade
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Bulk micromechanics Wafer properties important, KOH etching 54.7o walls SOI micromechanics DRIE for patterning, isotropic oxide etching for release Surface micromechanics Deposition of 2 µm thick layers, RIE of structural layer, isotropic etching of sacrificial layer
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