Performed by: Jonathan Silber Itzik Ben-Shushan Instructor: Isaschar walter המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering דו ” ח סיכום פרויקט Network On Chip Router חורף -אביב

Abstract המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 Traditionally, on-chip global communication has been addressed by shared-bus structures. However this method is limited in the amount of modules that can connect to the shared bus. Network on Chip replaces the bus and connects modules via specialized nodes that are connected by point to point links. The purposed NoC approach will provide a more efficient, high performance, on-chip communications for complex System on Chip (SoC) designs.

3 QNoC System description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Xilinx XUP Virtex™-II Pro Development System Router (part-A) PPC & peripherals (just as another module) Processing Module Processing Module Processing Module Router (part-A) Router (part-A) Router (part-A) PC – User Interface Through UART and Chipscope Analyzer QNoC 3

Specification המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Hardware : Virtex-II Pro XUP Development Board, with Xilinx Virtex-II Pro FPGA. Software Mentor Graphics - HDL Designer 2007 Xilinx - EDK 9.2 4

5 System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory QNoC based multi-core system Router 00 (address 0000) Interface to PPC through opb-ipif XOR With ‘1’ Calculator Inverter (Buffer) Calcu lating PC – User Interface Through UART and Chipscope Analyzer PLB PPC IPIF IPIC PPC - Running pre-defined code Chipscope Control+ILA’s OPB On-Board memory UART Router 01 (address 0100) Router 10 (address 0001) Router 11 (address 1010 QNoC Xilinx XUP Virtex™-II Pro Development System 5

System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 Data Control Data Control ROUTER Crossbar Input port West East South North Processing Unit Interface Module output port QNoC’s Router

System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 7 FIFO ROUTER PortInput CRT Switching SL Data In flits PREVIOUS ROUTER IN PATH / PROCESSING UNIT Buffer credits read/write Control Crossbar Data Per Service- Level Current Routing Table SL Read lines From output- ports Router Input Port

8 System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Router Crossbar (2X2) To Output Port From Input Port Routing DATA according to CRT From Input Port To Output port DATA + CRT DATA DATA + CRT CSIP SL1 SL2 SL1 SL2 CRT 8

9 System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 9 Router Output Port ROUTER OutputPort CSIP Buffer credits NBS CSIP NBS CSIP Buffer credits Round-Robin & control NEXT ROUTER IN PATH / PROCESSING UNIT Data In flits Switching SL Crossbar Currently Serviced Input Port Next Buffer State Data Per Service- Level Read lines To input- ports