By Wannarat Computer System Design Lecture 4 Wannarat Suntiamorntut

By Wannarat Part I : Single Data Path

By Wannarat Outline Design a Processor step by step Requirement of instruction set Components and clocking Testing Datapath Control Datapath

By Wannarat Five Component of Computer Datapath Control Processor MEMORYMEMORY Input Output

By Wannarat Performance Perspective Performance of machine is determined by CPI Processor Design : clock cycle time clock per instruction Single cycle processor : adv. : one clock cycle per instruction disadv. : long cycle time

By Wannarat Design Processor Step by Step 1. Analyze instruction set ==> Datapath requirement 2. Selection Set of datapath and establish clocking methodology 3. Assembly datapath meeting requirement 4. Analyze implementation of each instruction to determine setting of control 5. Assembly the control logic

By Wannarat MIPS Instruction Format

By Wannarat Step 1 ADDUrd, rs, rtSUBU rd, rs, rt ORI rt, rs, imm16

By Wannarat Step 1 lw rt, rs,imm16 sw rt, rs, imm16 beq rs, rt, imm16

By Wannarat RTL All instructions start by fetching Mem[PC] ADDU rd <= rs + rt;PC = PC + 4 SUBU rd <= rs + rt;PC = PC + 4 Ori rt <= rs + zero_ext(imm16);PC = PC + 4 LOAD rt <= mem[rs] + sign_ext(imm16); PC=PC + 4 STORE mem[rs] + sign_ext(imm16)<=rt; PC=PC+4 BEQ if rs = rt then PC=PC+sign_ext(imm16)||00 else PC = PC + 4

By Wannarat Step 1 : The requirement from instruction Memory Data & Instruction Register (32 x 32) Read rsRead rt Write rt or rd PC Extender Add and sub register or extend immediate Add 4 or extended immediate to PC

By Wannarat Step 2 : Components of datapath Combination Element Storage elements Clocking methodology

By Wannarat Combination Elements AdderMUX

By Wannarat Combination Elements ALU

By Wannarat Storage Element : Register Similar to D-flip/flop Write enable negated(0) : Data out won’t change asserted(1) : Data out will be data in

By Wannarat Register file Consist of 32 registers Ra select register to bus A Rb select register to bus B Rw select register to be written via bus W

By Wannarat Storage : Ideal Memory One Input One Output Memory word is selected by Address, Write enable = 1 then the data will be written Clock input : is a factor only during write operation During read operation : behaves on combination logic.

By Wannarat Clock Methodology

By Wannarat Step 3 : Register Transfer Requirements --> Datapath Assembly Instruction Fetch Read Operands and Execute Operation

By Wannarat Step 3 a : Instruction Fetch Unit Update PC : Sequence Code: PC <= PC + 4 Branch and Jump : PC <- something else

By Wannarat Step 3b : Add & Sub

By Wannarat Register-Register Timing

By Wannarat Step 3c :Logical Operations with Immed.

By Wannarat Step 3d: Load operations

By Wannarat Step 3e : Store Operations

By Wannarat Step 3f: Branch instruction beq rs, rt, imme16 mem[pc] equal <= rs = rt if (con eq 0) then PC<=PC+4+(signExt(imm16)x4); else PC <= PC + 4;

By Wannarat Datapath for Branch Operations

By Wannarat Put it all together

By Wannarat Abstract view of critical path

By Wannarat Step 4 : Control Path

By Wannarat Meaning of control signal Rs, Rt and Imme16 hardwire to datapath nPC_sel : 0 => PC PC PC PC <= PC signExt(Imm16) || 00

By Wannarat Meaning of control signals ExtOp : Zero, signMemWr:write memory ALUsrc: 0=>regB, 1=>imme Memtoreg:1=>mem ALUcrt : add, sub, orReqWr : write dest. Reg.

By Wannarat Control Signals

By Wannarat Step 5 : Logic for each control signal

By Wannarat Example : Load Flow

By Wannarat Abstract View of implementation

By Wannarat Next on Lecture 5