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ELEN 350 Single Cycle Datapath Adapted from the lecture notes of John Kubiatowicz(UCB) and Hank Walker (TAMU)

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1 ELEN 350 Single Cycle Datapath Adapted from the lecture notes of John Kubiatowicz(UCB) and Hank Walker (TAMU)

2 The Big Picture: The Performance Perspective °Performance of a machine is determined by: Instruction count Clock cycle time Clock cycles per instruction °Processor design (datapath and control) will determine: Clock cycle time Clock cycles per instruction °Single cycle processor: Advantage: One clock cycle per instruction Disadvantage: long cycle time CPI Inst. CountCycle Time

3 How to Design a Processor: step-by-step °1. Analyze instruction set => datapath requirements the meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers -possibly more datapath must support each register transfer °2. Select set of datapath components and establish clocking methodology °3. Assemble datapath meeting the requirements °4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. °5. Assemble the control logic

4 The MIPS Instruction Formats °All MIPS instructions are 32 bits long. The three instruction formats: R-type I-type J-type °The different fields are: op: operation of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of the jump instruction optarget address 02631 6 bits26 bits oprsrtrdshamtfunct 061116212631 6 bits 5 bits oprsrt immediate 016212631 6 bits16 bits5 bits

5 Step 1a: The MIPS-lite Subset °ADD and SUB addu rd, rs, rt subu rd, rs, rt °OR Immediate: ori rt, rs, imm16 °LOAD and STORE Word lw rt, rs, imm16 sw rt, rs, imm16 °BRANCH: beq rs, rt, imm16 oprsrtrdshamtfunct 061116212631 6 bits 5 bits oprsrtimmediate 016212631 6 bits16 bits5 bits oprsrtimmediate 016212631 6 bits16 bits5 bits oprsrtimmediate 016212631 6 bits16 bits5 bits

6 Logical Register Transfers °RTL gives the meaning of the instructions °All start by fetching the instruction op | rs | rt | rd | shamt | funct = MEM[ PC ] op | rs | rt | Imm16 = MEM[ PC ] inst Register Transfers adduR[rd] <– R[rs] + R[rt];PC <– PC + 4 subuR[rd] <– R[rs] – R[rt];PC <– PC + 4 oriR[rt] <– R[rs] | zero_ext(Imm16); PC <– PC + 4 lwR[rt] <– MEM[ R[rs] + sign_ext(Imm16)];PC <– PC + 4 swMEM[ R[rs] + sign_ext(Imm16) ] <– R[rt];PC <– PC + 4 beq if ( R[rs] == R[rt] ) then PC <– PC + 4 + sign_ext(Imm16)] || 00 else PC <– PC + 4

7 Step 1: Requirements of the Instruction Set °Memory instruction & data °Registers (32 x 32) read RS read RT Write RT or RD °PC °Extender °Add and Sub register or extended immediate °Add 4 or extended immediate to PC

8 Step 2: Components of the Datapath °Combinational Elements °Storage Elements Clocking methodology

9 Combinational Logic Elements (Basic Building Blocks) °Adder °MUX °ALU 32 A B Sum Carry 32 A B Result OP 32 A B Y Select Adder MUX ALU CarryIn

10 Verilog Implementation of Basic Blocks module adder(sum, carry_out, a, b, carry_in); input [31:0] a, b; input carry_in; output [31:0] sum; output carry_out; assign {carry_out, sum} = a+b; endmodule module mux(y, a, b, select); input [31:0] a, b; input select; output [31:0] y; assign y = (select) ? a: b; endmodule

11 Storage Element: Register (Basic Building Block) °Register Similar to the D Flip Flop except -32-bit input and output -Write Enable input Write Enable: -negated (0): Data Out will not change -asserted (1): Data Out will become Data In Clk Data In Write Enable 32 Data Out

12 Verilog Implementation of Basic Blocks module register(data_out, clk, data_in, write_en); input [31:0] data_in; input clk, write_en; output [31:0] data_out; reg [31:0] data_out; always @(posedge clk) begin if (write_en) data_out = data_in; end endmodule

13 Storage Element: Register File °Register File consists of 32 registers: Two 32-bit output busses: busA and busB One 32-bit input bus: busW °Register is selected by: RA (number) selects the register to put on busA (data) RB (number) selects the register to put on busB (data) RW (number) selects the register to be written via busW (data) when Write Enable is 1 °Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: -RA or RB valid => busA or busB valid after “access time.” Clk busW Write Enable 32 busA 32 busB 555 RWRARB 32 32-bit Registers

14 Storage Element: Idealized Memory °Memory (idealized) One input bus: Data In One output bus: Data Out °Memory word is selected by: Address selects the word to put on Data Out Write Enable = 1: address selects the memory word to be written via the Data In bus °Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: -Address valid => Data Out valid after “access time.” Clk Data In Write Enable 32 DataOut Address

15 Clocking Methodology (Simple View) °All storage elements are clocked by the same clock edge °CLK-to-Q + Longest Delay Path < Cycle Time °What is the longest path? Clk........................

16 Step 3: Assemble Datapath meeting our requirements °Register Transfer Requirements  Datapath Assembly °Instruction Fetch °Read Operands and Execute Operation

17 3a: Overview of the Instruction Fetch Unit °The common RTL operations Fetch the Instruction: mem[PC] Update the program counter: -Sequential Code: PC <- PC + 4 -Branch and Jump: PC <- “something else” 32 Instruction Word Address Instruction Memory PC Clk Next Address Logic

18 3b: Add & Subtract °R[rd] <- R[rs] op R[rt] Example: addu rd, rs, rt Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields ALUctr and RegWr: control logic after decoding the instruction 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers RsRtRd ALU oprsrtrdshamtfunct 061116212631 6 bits 5 bits

19 Register-Register Timing: One complete cycle 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers RsRtRd ALU Clk PC Rs, Rt, Rd, Op, Func Clk-to-Q ALUctr Instruction Memory Access Time Old ValueNew Value RegWrOld ValueNew Value Delay through Control Logic busA, B Register File Access Time Old ValueNew Value busW ALU Delay Old ValueNew Value Old ValueNew Value Old Value Register Write Occurs Here

20 3c: Logical Operations with Immediate °R[rt] <- R[rs] op ZeroExt[imm16] ] 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs ZeroExt Mux RtRd RegDst Mux 32 16 imm16 ALUSrc ALU 11 oprsrtimmediate 016212631 6 bits16 bits5 bits rd? immediate 0161531 16 bits 0 0 0 0 0 0 0 0 Rt?

21 3d: Load Operations °R[rt] <- Mem[R[rs] + SignExt[imm16]]Example: lw rt, rs, imm16 11 oprsrtimmediate 016212631 6 bits16 bits5 bits rd 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs RtRd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Clk Data In WrEn 32 Adr Data Memory 32 ALU MemWr Mu x W_Src ?? Rt?

22 3e: Store Operations °Mem[ R[rs] + SignExt[imm16] <- R[rt] ] Example: sw rt, rs, imm16 oprsrtimmediate 016212631 6 bits16 bits5 bits 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Clk Data In WrEn 32 Adr Data Memory MemWr ALU 32 Mu x W_Src

23 3f: The Branch Instruction °beqrs, rt, imm16 mem[PC]Fetch the instruction from memory Equal <- R[rs] == R[rt]Calculate the branch condition if (Equal)Calculate the next instruction’s address -PC <- PC + 4 + ( SignExt(imm16) x 4 ) else -PC <- PC + 4 oprsrtimmediate 016212631 6 bits16 bits5 bits

24 Datapath for Branch Operations °beq rs, rt, imm16Datapath generates condition (equal) oprsrtimmediate 016212631 6 bits16 bits5 bits 32 imm16 PC Clk 00 Adder Mux Adder 4 nPC_sel Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Equal? Cond PC Ext Inst Address

25 Putting it All Together: A Single Cycle Datapath imm16 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal Instruction 0 1 0 1 0 1 Imm16RdRtRs = Adder PC Clk 00 Mux 4 nPC_sel PC Ext Adr Inst Memory

26 An Abstract View of the Critical Path °Register file and ideal memory: The CLK input is a factor ONLY during write operation During read operation, behave as combinational logic: -Address valid => Output valid after “access time.” Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew Clk 5 RwRaRb 32 32-bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 16 Imm 32 A B Next Address

27 An Abstract View of the Implementation Data Out Clk 5 RwRaRb 32 32-bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 32 A B Next Address Control Datapath Control Signals Conditions

28 Recap: A Single Cycle Datapath °Rs, Rt, Rd and Imed16 hardwired into datapath from Fetch Unit °We have everything except control signals (underline) Today’s lecture will show you how to generate the control signals 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 MemWr ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt nPC_sel

29 Recap: Meaning of the Control Signals °nPC_MUX_sel: 0  PC <– PC + 4 1  PC <– PC + 4 + SignExt(Im16) || 00 °Later in lecture: higher-level connection between mux and branch cond Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_MUX_sel PC Ext imm16

30 Recap: Meaning of the Control Signals °ExtOp:“zero”, “sign” °ALUsrc:0  regB; 1  immed °ALUctr:“add”, “sub”, “or” °MemWr:1  write memory °MemtoReg:0  ALU; 1  Mem °RegDst:0  “rt”; 1  “rd” °RegWr:1  write register 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal 0 1 0 1 0 1 =

31 RTL: The Add Instruction °addrd, rs, rt mem[PC]Fetch the instruction from memory R[rd] <- R[rs] + R[rt]The actual operation PC <- PC + 4Calculate the next instruction’s address oprsrtrdshamtfunct 061116212631 6 bits 5 bits

32 Instruction Fetch Unit at the Beginning of Add °Fetch the instruction from Instruction memory: Instruction <- mem[PC] This is the same for all instructions PC Ext Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_MUX_sel imm16 Instruction

33 The Single Cycle Datapath during Add 32 ALUctr = Add Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = 1 Extender Mux 32 16 imm16 ALUSrc = 0 ExtOp = x Mux MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction °R[rd] <- R[rs] + R[rt] 0 1 0 1 01 Imm16RdRsRt oprsrtrdshamtfunct 061116212631 nPC_sel= +4

34 Clk Instruction Fetch Unit at the End of Add °PC <- PC + 4 This is the same for all instructions except: Branch and Jump Adr Inst Memory Adder PC 00 Mux 4 nPC_MUX_sel imm16 Instruction 0 1

35 The Single Cycle Datapath during Or Immediate °R[rt] <- R[rs] or ZeroExt[Imm16] oprsrtimmediate 016212631 32 ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = Extender Mux 32 16 imm16 ALUSrc = ExtOp = Mux MemtoReg = Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt nPC_sel =

36 The Single Cycle Datapath during Or Immediate 32 ALUctr = Or Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = 0 Extender Mux 32 16 imm16 ALUSrc = 1 ExtOp = 0 Mux MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction °R[rt] <- R[rs] or ZeroExt[Imm16] 0 1 0 1 01 Imm16RdRsRt oprsrtimmediate 016212631 nPC_sel= +4

37 The Single Cycle Datapath during Load 32 ALUctr = Add Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = 0 Extender Mux 32 16 imm16 ALUSrc = 1 ExtOp = 1 Mux MemtoReg = 1 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt °R[rt] <- Data Memory {R[rs] + SignExt[imm16]} oprsrtimmediate 016212631 nPC_sel= +4

38 The Single Cycle Datapath during Store °Data Memory {R[rs] + SignExt[imm16]} <- R[rt] oprsrtimmediate 016212631 32 ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = Extender Mux 32 16 imm16 ALUSrc = ExtOp = Mux MemtoReg = Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt nPC_sel =

39 The Single Cycle Datapath during Store 32 ALUctr = Add Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = x Extender Mux 32 16 imm16 ALUSrc = 1 ExtOp = 1 Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 1 ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt °Data Memory {R[rs] + SignExt[imm16]} <- R[rt] oprsrtimmediate 016212631 nPC_sel= +4

40 The Single Cycle Datapath during Branch 32 ALUctr =Sub Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = x Extender Mux 32 16 imm16 ALUSrc = 0 ExtOp = x Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt °if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0 oprsrtimmediate 016212631 nPC_sel= “Br”

41 Instruction Fetch Unit at the End of Branch °if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4 oprsrtimmediate 016212631 °What is encoding of nPC_sel? Direct MUX select? Branch / not branch °Let’s choose second option Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction 0 1 Zero nPC_MUX_sel

42 Step 4: Given Datapath: RTL -> Control ALUctr RegDst ALUSrc ExtOp MemtoRegMemWr Zero Instruction Imm16RdRsRt nPC_sel Adr Inst Memory DATA PATH Control Op Fun RegWr

43 A Summary of Control Signals inst Register Transfer ADDR[rd] <– R[rs] + R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4” SUBR[rd] <– R[rs] – R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4” ORiR[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4” LOADR[rt] <– MEM[ R[rs] + sign_ext(Imm16)];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4” STOREMEM[ R[rs] + sign_ext(Imm16)] <– R[rs];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4” BEQif ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 nPC_sel = “Br”, ALUctr = “sub”

44 A Summary of the Control Signals addsuborilwswbeqjump RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr 1 0 0 1 0 0 0 x Add 1 0 0 1 0 0 0 x Subtract 0 1 0 1 0 0 0 0 Or 0 1 1 1 0 0 0 1 Add x 1 x 0 1 0 0 1 x 0 x 0 0 1 0 x Subtract x x x 0 0 0 1 x xxx optarget address oprsrtrdshamtfunct 061116212631 oprsrt immediate R-type I-type J-type add, sub ori, lw, sw, beq jump func op000000 001101100011101011000100000010 Appendix A 100000See100010We Don’t Care :-)

45 The Concept of Local Decoding Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 ALU

46 The Encoding of ALUop °In this exercise, ALUop has to be 2 bits wide to represent: (1) “R-type” instructions “I-type” instructions that require the ALU to perform: -(2) Or, (3) Add, and (4) Subtract °To implement the full MIPS ISA, ALUop has to be 3 bits to represent: (1) “R-type” instructions “I-type” instructions that require the ALU to perform: -(2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi) Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 R-typeorilwswbeqjump ALUop (Symbolic)“R-type”OrAdd Subtract xxx ALUop 1 000 100 00 0 01 xxx

47 The Decoding of the “func” Field R-typeorilwswbeqjump ALUop (Symbolic)“R-type”OrAdd Subtract xxx ALUop 1 000 100 00 0 01 xxx Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 oprsrtrdshamtfunct 061116212631 R-type funct Instruction Operation 10 0000 10 0010 10 0100 10 0101 10 1010 add subtract and or set-on-less-than ALUctr ALU Operation 000 001 010 110 111 And Or Add Subtract Set-on-less-than P. 286 text: ALUctr ALU

48 The Truth Table for ALUctr R-typeorilwswbeq ALUop (Symbolic) “R-type”OrAdd Subtract ALUop 1 000 100 00 0 01 funct Instruction Op. 0000 0010 0100 0101 1010 add subtract and or set-on-less-than

49 The Logic Equation for ALUctr ALUopfunc bit ALUctr 0x1xxxx1 1xx00101 1xx10101 °ALUctr = !ALUop & ALUop + ALUop & !func & func & !func This makes func a don’t care

50 The Logic Equation for ALUctr ALUopfunc bit 000xxxx1 ALUctr 0x1xxxx1 1xx00001 1xx00101 1xx10101 °ALUctr = !ALUop & !ALUop + ALUop & !func & !func

51 The Logic Equation for ALUctr ALUopfunc bit ALUctr 01xxxxx1 1xx01011 1xx10101 °ALUctr = !ALUop & ALUop + ALUop & !func & func & !func & func + ALUop & func & !func & func & !func

52 The ALU Control Block ALU Control (Local) func 3 6 ALUop ALUctr 3 °ALUctr = !ALUop & ALUop + ALUop & !func & func & !func °ALUctr = !ALUop & !ALUop + ALUop & !func & !func °ALUctr = !ALUop & ALUop + ALUop & !func & func & !func & func + ALUop & func & !func & func & !func

53 Step 5: Logic for each control signal °nPC_sel <= (OP == `BEQ) ? `Br : `plus4; °ALUsrc <=(OP == `Rtype) ? `regB : `immed; °ALUctr<= (OP == `Rtype`) ? funct : (OP == `ORi) ? `ORfunction : (OP == `BEQ) ? `SUBfunction : `ADDfunction; °ExtOp <= _____________ °MemWr<= _____________ °MemtoReg<= _____________ °RegWr:<=_____________ °RegDst:<= _____________

54 Step 5: Logic for each control signal °nPC_sel <= (OP == `BEQ) ? `Br : `plus4; °ALUsrc <=(OP == `Rtype) ? `regB : `immed; °ALUctr<= (OP == `Rtype`) ? funct : (OP == `ORi) ? `ORfunction : (OP == `BEQ) ? `SUBfunction : `ADDfunction; °ExtOp <= (OP == `ORi) : `ZEROextend : `SIGNextend; °MemWr<= (OP == `Store) ? 1 : 0; °MemtoReg<= (OP == `Load) ? 1 : 0; °RegWr:<= ((OP == `Store) || (OP == `BEQ)) ? 0 : 1; °RegDst:<= ((OP == `Load) || (OP == `ORi)) ? 0 : 1;

55 The “Truth Table” for the Main Control R-typeorilwswbeqjump RegDst ALUSrc MemtoReg RegWrite MemWrite nPC_sel Jump ExtOp ALUop (Symbolic) 1 0 0 1 0 0 0 x “R-type” 0 1 0 1 0 0 0 0 Or 0 1 1 1 0 0 0 1 Add x 1 x 0 1 0 0 1 x 0 x 0 0 1 0 x Subtract x x x 0 0 0 1 x xxx op00 000000 110110 001110 101100 010000 0010 ALUop 1000 0 x 0100 0 x 0000 1 x Main Control op 6 ALU Control (Local) func 3 6 ALUop ALUctr 3RegDst ALUSrc :

56 The “Truth Table” for RegWrite R-typeorilwswbeqjump RegWrite111000 op00 000000 110110 001110 101100 010000 0010 °RegWrite = R-type + ori + lw = !op & !op & !op & !op & !op & !op (R-type) + !op & !op & op & op & !op & op (ori) + op & !op & !op & !op & op & op (lw) RegWrite

57 PLA Implementation of the Main Control RegWrite ALUSrc MemtoReg MemWrite Branch Jump RegDst ExtOp ALUop

58 Putting it All Together: A Single Cycle Processor 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 MemWr ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt Main Control op 6 ALU Control func 6 3 ALUop ALUctr 3 RegDst ALUSrc : Instr nPC_sel

59 Recap: An Abstract View of the Critical Path (Load) °Register file and ideal memory: The CLK input is a factor ONLY during write operation During read operation, behave as combinational logic: -Address valid => Output valid after “access time.” Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew Clk 5 RwRaRb 32 32-bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 16 Imm 32 A B Next Address

60 Worst Case Timing (Load) Clk PC Rs, Rt, Rd, Op, Func Clk-to-Q ALUctr Instruction Memory Access Time Old ValueNew Value RegWrOld ValueNew Value Delay through Control Logic busA Register File Access Time Old ValueNew Value busB ALU Delay Old ValueNew Value Old ValueNew Value Old Value ExtOpOld ValueNew Value ALUSrcOld ValueNew Value MemtoRegOld ValueNew Value AddressOld ValueNew Value busWOld ValueNew Delay through Extender & Mux Register Write Occurs Data Memory Access Time

61 Drawback of this Single Cycle Processor °Long cycle time: Cycle time must be long enough for the load instruction: PC’s Clock -to-Q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew °Cycle time for load is much longer than needed for all other instructions

62 °Single cycle datapath => CPI=1, CCT => long °5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic °Control is the hard part °MIPS makes control easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Summary Control Datapath Memory Processor Input Output

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