1. EEM 486: Computer Architecture Designing a Single Cycle Datapath

2. The Big Picture: Where are We Now? The Five Classic Components of a Computer Today’s Topic: Design a Single Cycle Processor Control Datapath Memory Processor Input Output

3. The Big Picture: The Performance Perspective Performance of a machine is determined by: ◦ Instruction count ◦ Clock cycle time ◦ Clock cycles per instruction Processor design (datapath and control) will determine: ◦ Clock cycle time ◦ Clock cycles per instruction Today: ◦ Single cycle processor:  Advantage: One clock cycle per instruction  Disadvantage: long cycle time CPI Inst. CountCycle Time

4. How to Design a Processor: Step-by-Step 1. Analyze instruction set => datapath requirements ◦ Meaning of each instruction is given by the register transfers ◦ Datapath must include storage element for ISA registers  possibly more ◦ Datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer 5. Assemble the control logic

5. The MIPS Instruction Formats The three instruction formats: ◦ R-type ◦ I-type ◦ J-type The different fields are: ◦ op: operation of the instruction ◦ rs, rt, rd: the source and destination register specifiers ◦ shamt: shift amount ◦ funct: selects the variant of the operation in the “op” field ◦ address / immediate: address offset or immediate value ◦ target address: target address of the jump instruction optarget address 02631 6 bits26 bits oprsrtrdshamtfunct 061116212631 6 bits 5 bits oprsrt immediate 016212631 6 bits16 bits5 bits

6. Step 1a: The MIPS-lite Subset for Today ADD/SUB ◦ addU rd, rs, rt ◦ subU rd, rs, rt OR Immediate: ◦ ori rt, rs, imm16 LOAD/STORE Word ◦ lw rt, rs, imm16 ◦ sw rt, rs, imm16 BRANCH ◦ beq rs, rt, imm16 oprsrtrdshamtfunct 061116212631 6 bits 5 bits oprsrtimmediate 016212631 6 bits16 bits5 bits oprsrtimmediate 016212631 6 bits16 bits5 bits oprsrtimmediate 016212631 6 bits16 bits5 bits

7. Logical Register Transfers RTL gives the meaning of the instructions All start by fetching the instruction op | rs | rt | rd | shamt | funct = MEM[ PC ] op | rs | rt | Imm16 = MEM[ PC ] inst Register Transfers ADDUR[rd] <– R[rs] + R[rt];PC <– PC + 4 SUBUR[rd] <– R[rs] – R[rt];PC <– PC + 4 ORiR[rt] <– R[rs] | zero_ext(Imm16); PC <– PC + 4 LOADR[rt] <– MEM[ R[rs] + sign_ext(Imm16)];PC <– PC + 4 STOREMEM[ R[rs] + sign_ext(Imm16) ] <– R[rt];PC <– PC + 4 BEQif ( R[rs] == R[rt] ) then PC <– PC + 4 + [sign_ext(Imm16) || 00] else PC <– PC + 4

8. Step 1: Requirements of the Instruction Set Memory ◦ instruction & data Registers (32 x 32) ◦ read RS ◦ read RT ◦ Write RT or RD PC Extender Add and Sub registers or register and extended immediate Logical Or of a register and extended immediate Add 4 or extended immediate to PC

9. Step 2: Components of the Datapath Combinational Elements Storage Elements Clocking methodology

10. Combinational Logic Elements (Basic Building Blocks) Adder MUX ALU 32 A B Sum Carry 32 A B Result OP 32 A B Y Select Adder MUX ALU CarryIn

11. Storage Element: Register (Basic Building Block) Register ◦ Similar to the D Flip Flop except  N-bit input and output  Write Enable input ◦ Write Enable:  Negated (0): Data Out will not change  Asserted (1): Data Out becomes Data In Clk Data In Write Enable NN Data Out

12. Storage Element: Register File Register File consists of 32 registers: ◦ Two 32-bit output busses: busA and busB ◦ One 32-bit input bus: busW Register is selected by: ◦ RA (number) selects the register to put on busA (data) ◦ RB (number) selects the register to put on busB (data) ◦ RW (number) selects the register to be written via busW (data) when Write Enable is 1 Clock input (CLK) ◦ The CLK input is a factor ONLY during write operation ◦ During read operation, behaves as a combinational logic block:  RA or RB valid => busA or busB valid after “access time.” Clk busW Write Enable 32 busA 32 busB 555 RWRARB 32 32-bit Registers

13. Storage Element: Idealized Memory Memory (idealized) ◦ One input bus: Data In ◦ One output bus: Data Out Memory word is selected by: ◦ Address selects the word to put on Data Out ◦ Write Enable = 1: address selects the memory word to be written via the Data In bus Clock input (CLK) ◦ The CLK input is a factor ONLY during write operation ◦ During read operation, behaves as a combinational logic block:  Address valid => Data Out valid after “access time.” Clk Data In Write Enable 32 DataOut Address

14. Clocking Methodology (Just in case) All storage elements are clocked by the same clock edge Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew (CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold Time........................ Clk Don’t Care SetupHoldSetupHold

15. Step 3: Assemble Datapath Meeting Requirements Register Transfer Requirements  Datapath Assembly Instruction Fetch Read Operands and Execute Operation

16. 3a: Overview of the Instruction Fetch Unit The common RTL operations ◦ Fetch the Instruction: mem[PC] ◦ Update the program counter:  Sequential Code: PC  PC + 4  Branch and Jump: PC  “something else” 32 Instruction Word Address Instruction Memory PC Clk Next Address Logic

17. 3b: Add & Subtract R[rd]  R[rs] op R[rt] Example: addU rd, rs, rt ◦ Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields ◦ ALUctr and RegWr: control logic after decoding the instruction 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers RsRtRd ALU oprsrtrdshamtfunct 061116212631 6 bits 5 bits

18. Register-Register Timing: One complete cycle 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers RsRtRd ALU Clk PC Rs, Rt, Rd, Op, Func Clk-to-Q ALUctr Instruction Memory Access Time Old ValueNew Value RegWrOld ValueNew Value Delay through Control Logic busA, B Register File Access Time Old ValueNew Value busW ALU Delay Old ValueNew Value Old ValueNew Value Old Value Register Write Occurs Here

19. 3c: Logical Operations with Immediate R[rt]  R[rs] op ZeroExt[imm16] oprsrtimmediate 016212631 6 bits16 bits5 bits 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs ZeroExt Mux RtRd RegDst Mux 32 16 imm16 ALUSrc ALU Rt?

20. 3d: Load Operations R[rt]  Mem[R[rs] + SignExt[imm16]] E.g.: lw rt, rs, imm16 oprsrtimmediate 016212631 6 bits16 bits5 bits 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs RtRd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Clk Data In WrEn 32 Adr Data Memory 32 ALU MemWr Mu x W_Src ?? Rt?

21. 3e: Store Operations Mem[ R[rs] + SignExt[imm16] ]  R[rt] E.g.: sw rt, rs, imm16 oprsrtimmediate 016212631 6 bits16 bits5 bits 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Clk Data In WrEn 32 Adr Data Memory MemWr ALU 32 Mu x W_Src

22. 3f: The Branch Instruction beqrs, rt, imm16 ◦ mem[PC]Fetch the instruction from memory ◦ Equal  R[rs] == R[rt]Calculate the branch condition ◦ if (Equal)Calculate the next instruction’s address  PC  PC + 4 + ( SignExt(imm16) x 4 ) ◦ else  PC  PC + 4 oprsrtimmediate 016212631 6 bits16 bits5 bits

23. Datapath for Branch Operations beq rs, rt, imm16Datapath generates condition (equal) oprsrtimmediate 016212631 6 bits16 bits5 bits 32 imm16 PC Clk 00 Adder Mux Adder 4 nPC_sel Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Equal? Cond PC Ext Inst Address

24. Putting it All Together: A Single Cycle Datapath imm16

25. A Single Cycle Datapath

26. An Abstract View of the Critical Path Register file and ideal memory: ◦ The CLK input is a factor ONLY during write operation ◦ During read operation, behave as combinational logic:  Address valid => Output valid after “access time.” Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew Clk 5 RwRaRb 32 32-bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 16 Imm 32 A B Next Address

27. An Abstract View of the Implementation Data Out Clk 5 RwRaRb 32 32-bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 32 A B Next Address Control Datapath Control Signals Conditions

28. Steps 4 & 5: Implement the control Next time

29. Summary 5 steps to design a processor ◦ 1. Analyze instruction set => datapath requirements ◦ 2. Select set of datapath components & establish clock methodology ◦ 3. Assemble datapath meeting the requirements ◦ 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. ◦ 5. Assemble the control logic MIPS makes it easier ◦ Instructions same size ◦ Source registers always in same place ◦ Immediates same size, location ◦ Operations always on registers/immediates Single cycle datapath => CPI=1, CCT => long Next time: implementing control