1. Datorteknik DatapathControl bild 1 Designing a Single Cycle Datapath & Datapath Control

2. Datorteknik DatapathControl bild 2 The Performance Perspective Performance of a machine is determined by: –Instruction count –Clock cycle time –Clock cycles per instruction Processor design (datapath and control) will determine: –Clock cycle time –Clock cycles per instruction Single cycle processor: Advantage: One clock cycle per instruction Disadvantage: long cycle time CPI Inst. CountCycle Time

3. Datorteknik DatapathControl bild 3 How to Design a Processor: step-by-step 1. Analyze instruction set => datapath requirements –the meaning of each instruction is given by the register transfers –datapath must include storage element for ISA registers possibly more –datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic

4. Datorteknik DatapathControl bild 4 The MIPS Instruction Formats All MIPS instructions are 32 bits long. The three instruction formats: –R-type –I-type –J-type The different fields are: –op: operation of the instruction –rs, rt, rd: the source and destination register specifiers –shamt: shift amount –funct: selects the variant of the operation in the “op” field –address / immediate: address offset or immediate value –target address: target address of the jump instruction optarget address 02631 6 bits26 bits oprsrtrdshamtfunct 061116212631 6 bits 5 bits oprsrt immediate 016212631 6 bits16 bits5 bits

5. Datorteknik DatapathControl bild 5 The MIPS-lite Subset for today ADD and SUB –addU rd, rs, rt –subU rd, rs, rt OR Immediate: –ori rt, rs, imm16 LOAD and STORE Word –lw rt, rs, imm16 –sw rt, rs, imm16 BRANCH: –beq rs, rt, imm16 oprsrtrdshamtfunct 061116212631 6 bits 5 bits oprsrtimmediate 016212631 6 bits16 bits5 bits oprsrtimmediate 016212631 6 bits16 bits5 bits oprsrtimmediate 016212631 6 bits16 bits5 bits

6. Datorteknik DatapathControl bild 6 Logical Register Transfers RTL gives the meaning of the instructions All start by fetching the instruction op | rs | rt | rd | shamt | funct = MEM[ PC ] op | rs | rt | Imm16 = MEM[ PC ] inst Register Transfers ADDUR[rd] <– R[rs] + R[rt];PC <– PC + 4 SUBUR[rd] <– R[rs] – R[rt];PC <– PC + 4 ORiR[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 LOADR[rt] <– MEM[ R[rs] + sign_ext(Imm16)];PC <– PC + 4 STOREMEM[ R[rs] + sign_ext(Imm16) ] <– R[rt];PC <– PC + 4 BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4

7. Datorteknik DatapathControl bild 7 Requirements of the Instruction Set Memory –instruction & data Registers (32 x 32) –read RS –read RT –Write RT or RD PC Extender Add and Sub register or extended immediate Add 4 or extended immediate to PC

8. Datorteknik DatapathControl bild 8 Components of the Datapath Combinational Elements Storage Elements –Clocking methodology

9. Datorteknik DatapathControl bild 9 Combinational Building Blocks 32 A B Y Select MUX 32 A B Result OPOP ALU 32 A B Sum Carry Adder CarryIn Adder MUX ALU

10. Datorteknik DatapathControl bild 10 Storage Element (Register) Register –Similar to the D Flip Flop except N-bit input and output Write Enable input –Write Enable: negated (0): Data Out will not change asserted (1): Data Out will become Data In Clk Data In Write Enable NN Data Out

11. Datorteknik DatapathControl bild 11 Storage Element: Register File Register File consists of 32 registers: –Two 32-bit output busses: busA and busB –One 32-bit input bus: busW Register is selected by: –RA (number) selects the register to put on busA (data) –RB (number) selects the register to put on busB (data) –RW (number) selects the register to be written via busW (data) when Write Enable is 1 Clock input (CLK) –The CLK input is a factor ONLY during write operation –During read operation, behaves as a combinational logic block: RA or RB valid => busA or busB valid after “access time.” Clk busW Write Enable 32 busA 32 busB 555 RWRARB 32 32-bit Registers

12. Datorteknik DatapathControl bild 12 Storage Element: Idealized Memory Memory (idealized) –One input bus: Data In –One output bus: Data Out Memory word is selected by: –Address selects the word to put on Data Out –Write Enable = 1: address selects the memory word to be written via the Data In bus Clock input (CLK) –The CLK input is a factor ONLY during write operation –During read operation, behaves as a combinational logic block: Address valid => Data Out valid after “access time.” Clk Data In Write Enable 32 DataOut Address

13. Datorteknik DatapathControl bild 13 Clocking Methodology All storage elements are clocked by the same clock edge Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew (CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold Time........................ Clk Don’t Care SetupHoldSetupHold

14. Datorteknik DatapathControl bild 14 Step 3 Register Transfer Requirements –> Datapath Assembly Instruction Fetch Read Operands and Execute Operation

15. Datorteknik DatapathControl bild 15 Overview of the Instruction Fetch Unit The common RTL operations –Fetch the Instruction: mem[PC] –Update the program counter: Sequential Code: PC <- PC + 4 Branch and Jump: PC <- “something else” 32 Instruction Word Address Instruction Memory PC Clk Next Address Logic

16. Datorteknik DatapathControl bild 16 Add & Subtract R[rd] <- R[rs] op R[rt] Example: addU rd, rs, rt –Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields –ALUctr and RegWr: control logic after decoding the instruction 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers RsRtRd ALU oprsrtrdshamtfunct 061116212631 6 bits 5 bits

17. Datorteknik DatapathControl bild 17 Register-Register Timing 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers RsRtRd ALU Clk PC Rs, Rt, Rd, Op, Func Clk-to-Q ALUctr Instruction Memory Access Time Old ValueNew Value RegWrOld ValueNew Value Delay through Control Logic busA, B Register File Access Time Old ValueNew Value busW ALU Delay Old ValueNew Value Old ValueNew Value Old Value Register Write Occurs Here

18. Datorteknik DatapathControl bild 18 Logical Operations with Immediate R[rt] <- R[rs] op ZeroExt[imm16] ] 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs RtRd RegDst ZeroExt Mux 32 16 imm16 ALUSrc ALU 11 oprsrtimmediate 016212631 6 bits16 bits5 bits rd? immediate 0161531 16 bits 0 0 0 0 0 0 0 0

19. Datorteknik DatapathControl bild 19 Load Operations R[rt] <- Mem[R[rs] + SignExt[imm16 Example: lw rt, rs, imm16 11 oprsrtimmediate 016212631 6 bits16 bits5 bits rd 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs RtRd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Clk Data In WrEn 32 Adr Data Memory 32 ALU MemWr M ux W_Src

20. Datorteknik DatapathControl bild 20 Store Operations Mem[ R[rs] + SignExt[imm16] <- R[rt] ] –Example: sw rt, rs, imm16 oprsrtimmediate 016212631 6 bits16 bits5 bits 32 ALUct r Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Clk Data In WrEn 32 Adr Data Memory MemWr ALU 32 M ux W_Src

21. Datorteknik DatapathControl bild 21 The Branch Instruction beqrs, rt, imm16 –mem[PC]Fetch the instruction from memory –Equal <- R[rs] == R[rt]Calculate the branch condition –if (COND eq 0)Calculate the next instruction’s address PC <- PC + 4 + ( SignExt(imm16) x 4 ) else PC <- PC + 4 oprsrtimmediate 016212631 6 bits16 bits5 bits

22. Datorteknik DatapathControl bild 22 Datapath for Branch Operations beq rs, rt, imm16Datapath generates condition (equal) oprsrtimmediate 016212631 6 bits16 bits5 bits 32 imm16 PC Clk 00 Adder Mux Adder 4 nPC_sel Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Equal? Cond PC Ext Inst Address

23. Datorteknik DatapathControl bild 23 A Single Cycle Datapath

24. Datorteknik DatapathControl bild 24 An Abstract View of the Critical Path Register file and ideal memory: –The CLK input is a factor ONLY during write operation –During read operation, behave as combinational logic: Address valid => Output valid after “access time.” Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew Clk 5 RwRaRb 32 32-bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 16 Imm 32 A B Next Address

25. Datorteknik DatapathControl bild 25 Given Datapath: RTL -> Control ALUctr RegDst ALUSrc ExtOp MemtoRegMemWr Equal Instruction Imm16RdRsRt nPC_sel Adr Inst Memory DATA PATH Control Op Fun RegWr

26. Datorteknik DatapathControl bild 26 Meaning of the Control Signals 1 Rs, Rt, Rd and Imed16 hardwired into datapath nPC_sel: 0 => PC <– PC + 4; 1 => PC <– PC + 4 + SignExt(Im16) || 00 Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel PC Ext imm16

27. Datorteknik DatapathControl bild 27 Meaning of the Control Signals 2 ExtOp:“zero”, “sign” ALUsrc:0 => regB; 1 => immed ALUctr:“add”, “sub”, “or” MemWr:write memory MemtoReg:1 => Mem RegDst:0 => “rt”; 1 => “rd” RegWr:write dest register

28. Datorteknik DatapathControl bild 28 Control Signals inst Register Transfer ADDR[rd] <– R[rs] + R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4” SUBR[rd] <– R[rs] – R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4” ORiR[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4” LOADR[rt] <– MEM[ R[rs] + sign_ext(Imm16)];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4” STOREMEM[ R[rs] + sign_ext(Imm16)] <– R[rs];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4” BEQif ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 nPC_sel = EQUAL, ALUctr = “sub”

29. Datorteknik DatapathControl bild 29 Example: Load Instruction 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal Instruction 0 1 0 1 0 1 Imm16RdRtRs = imm16 Adder PC Clk 00 Mux 4 nPC_sel PC Ext Adr Inst Memory sign ext add rt +4

30. Datorteknik DatapathControl bild 30 An Abstract View of the Implementation Logical vs. Physical Structure Data Out Clk 5 RwRaRb 32 32-bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 32 A B Next Address Control Datapath Control Signals Conditions

31. Datorteknik DatapathControl bild 31 A Real MIPS Datapath (CNS T0)

32. Datorteknik DatapathControl bild 32 Instruction Fetch Unit at the Beginning of Add Fetch the instruction from Instruction memory: Instruction <- mem[PC] –This is the same for all instructions PC Ext Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction

33. Datorteknik DatapathControl bild 33 The Single Cycle Datapath during Add R[rd] <- R[rs] + R[rt] oprsrtrdshamtfunct 061116212631

34. Datorteknik DatapathControl bild 34 Instruction Fetch Unit at the End of Add PC <- PC + 4 –This is the same for all instructions except: Branch and Jump Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction

35. Datorteknik DatapathControl bild 35 The Single Cycle Datapath during Or Immediate R[rt] <- R[rs] or ZeroExt[Imm16] oprsrtimmediate 016212631

36. Datorteknik DatapathControl bild 36 The Single Cycle Datapath during Or Immediate R[rt] <- R[rs] or ZeroExt[Imm16] oprsrtimmediate 016212631

37. Datorteknik DatapathControl bild 37 The Single Cycle Datapath during Load R[rt] <- Data Memory {R[rs] + SignExt[imm16]} oprsrtimmediate 016212631

38. Datorteknik DatapathControl bild 38 The Single Cycle Datapath during Store Data Memory {R[rs] + SignExt[imm16]} <- R[rt] oprsrtimmediate 016212631

39. Datorteknik DatapathControl bild 39 The Single Cycle Datapath during Store Data Memory {R[rs] + SignExt[imm16]} <- R[rt] oprsrtimmediate 016212631

40. Datorteknik DatapathControl bild 40 The Single Cycle Datapath during Branch if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0 oprsrtimmediate 016212631

41. Datorteknik DatapathControl bild 41 Instruction Fetch Unit at the End of Branch if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 else PC = PC + 4 oprsrtimmediate 016212631 Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction

42. Datorteknik DatapathControl bild 42 Given Datapath: RTL -> Control ALUctr RegDst ALUSrc ExtOp MemtoRegMemWr Equal Instruction Imm16RdRtRs nPC_sel Adr Inst Memory DATA PATH Control Op Fun RegWr

43. Datorteknik DatapathControl bild 43 A Summary of Control Signals inst Register Transfer ADDR[rd] <– R[rs] + R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4” SUBR[rd] <– R[rs] – R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4” ORiR[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4” LOADR[rt] <– MEM[ R[rs] + sign_ext(Imm16)];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4” STOREMEM[ R[rs] + sign_ext(Imm16)] <– R[rs];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4” BEQif ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 nPC_sel = “Br”, ALUctr = “sub”

44. Datorteknik DatapathControl bild 44 A Summary of the Control Signals optarget address oprsrtrdshamtfunct 061116212631 oprsrt immediate R-type I-type J-type add, sub ori, lw, sw, beq jump addsuborilwswbeqjump RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr 1 0 0 1 0 0 0 x Add 1 0 0 1 0 0 0 x Subtract 0 1 0 1 0 0 0 0 Or 0 1 1 1 0 0 0 1 Add x 1 x 0 1 0 0 1 x 0 x 0 0 1 0 x Subtract x x x 0 0 0 1 x xxx func op00 0000 00 110110 001110 101100 010000 0010 Appendix A 10 0000See10 0010We Don’t Care :-)

45. Datorteknik DatapathControl bild 45 The Concept of Local Decoding Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 ALU

46. Datorteknik DatapathControl bild 46 The Encoding of ALUop In this exercise, ALUop has to be 2 bits wide to represent: (1) “R-type” instructions “I-type” instructions that require the ALU to perform: (2) Or, (3) Add, and (4) Subtract To implement the full MIPS ISA, ALUop has to be 3 bits to represent: (1) “R-type” instructions “I-type” instructions that require the ALU to perform: (2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi) Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 R-typeorilwswbeqjump ALUop (Symbolic)“R-type”OrAdd Subtract xxx ALUop 1 000 100 00 0 01 xxx

47. Datorteknik DatapathControl bild 47 The Decoding of the “func” Field R-typeorilwswbeqjump ALUop (Symbolic)“R-type”OrAdd Subtract xxx ALUop 1 000 100 00 0 01 xxx Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 oprsrtrdshamtfunct 061116212631 R-type funct Instruction Operation 10 0000 10 0010 10 0100 10 0101 10 1010 add subtract and or set-on-less-than ALUctr ALU Operation 000 001 010 110 111 Add Subtract And Or Set-on-less-than Recall ALU ( P. 286 text): ALUc tr ALU

48. Datorteknik DatapathControl bild 48 Logic for each control signal nPC_sel <= if (OP == BEQ) then EQUAL else 0 ALUsrc <=if (OP == “Rtype”) then “regB” else “immed” ALUctr<= if (OP == “Rtype”) then funct elseif (OP == ORi) then “OR” elseif (OP == BEQ) then “sub” else “add” ExtOp <= if (OP == ORi) then “zero” else “sign” MemWr<= (OP == Store) MemtoReg<= (OP == Load) RegWr:<= if ((OP == Store) || (OP == BEQ)) then 0 else 1 RegDst:<= if ((OP == Load) || (OP == ORi)) then 0 else 1

49. Datorteknik DatapathControl bild 49 The “Truth Table” for the Main Control Main Control op 6 ALU Control (Local) func 3 6 ALUop ALUctr 3 RegDst ALUSrc :

50. Datorteknik DatapathControl bild 50 PLA Implementation of the Main Control op.... op.. op.. op.. op.. R-typeorilwswbeqjump RegWrite ALUSrc MemtoReg MemWrite Branch Jump RegDst ExtOp ALUop

51. Datorteknik DatapathControl bild 51 Putting it All Together: A Single Cycle Processor

52. Datorteknik DatapathControl bild 52 Drawback of this Single Cycle Processor Long cycle time: –Cycle time must be long enough for the load instruction: PC’s Clock -to-Q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew Cycle time for load is much longer than needed for all other instructions

53. Datorteknik DatapathControl bild 53 °Single cycle datapath => CPI=1, CCT => long °5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic °Control is the hard part °MIPS makes control easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Control Datapath Memory Processor Input Output Summary