Prof. Joongho Choi CMOS SEQUENTIAL CIRCUIT DESIGN Integrated Circuits Spring 2001 Dept. of ECE University of Seoul
Prof. Joongho Choi Combinational vs. Sequential Logic Combinational Logic OUT(t) IN(t) Sequential Logic OUT(t) IN(t) IN(t-kT) OUT(t-kT) Positive Feedback Charge on Cap. Positive Feedback Charge on Cap.
Prof. Joongho Choi Sequential Logic w/ Positive Feedback Two Inverters in Positive Feedback STATIC
Prof. Joongho Choi Bi-stability Transition Region Stable Regions Slope (Gain) >1
Prof. Joongho Choi SR Latch NOR-Based S R Q S R Q S R QQ Q Q S R Q Q Q S R Q S R Q Q Q Q Q Q NAND-Based
Prof. Joongho Choi JK Flip-Flop LL H H H ? HLHL L L H L L H H H H Q Q =H
Prof. Joongho Choi T-FF & D-FF
Prof. Joongho Choi Race Problem of Latch
Prof. Joongho Choi Master/Slave Flip-Flop masterslave H L H H L L H L One-Catching Level-Sensitive Input Data =High One-Catching Level-Sensitive Input Data =High
Prof. Joongho Choi Edge-Triggered Operation 1
Prof. Joongho Choi Edge-Triggered Operation 2
Prof. Joongho Choi Flip-Flop Timing Constraints Setup Time t setup Hold Time t hold Propagation Delay t pFF
Prof. Joongho Choi Flip-Flop Timing Example T > t pFF + t p,comb + t setup FF’s LOGIC t p,comb QY
Prof. Joongho Choi CMOS Latches
Prof. Joongho Choi Pseudo-Static D-Latch =High (Data I/O) =Low (Data Store)
Prof. Joongho Choi M/S D-FF (pseudo-Static) =High New Data In & Previous Data Store =Low New Data Out & New Data Store
Prof. Joongho Choi M/S D-FF (pseudo-Static) Problem
Prof. Joongho Choi M/S D-FF Problem Solution Non-Overlapping 2-Phase Clocks
Prof. Joongho Choi Dynamic M/S D-FF