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Flip-Flops Section 4.3 Mano & Kime. D Latch Q !Q CLK D !S !R S R 0 1 1 1 1 0 X 0 Q 0 !Q 0 D CLK Q !Q Note that Q follows D when the clock in high, and.

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Presentation on theme: "Flip-Flops Section 4.3 Mano & Kime. D Latch Q !Q CLK D !S !R S R 0 1 1 1 1 0 X 0 Q 0 !Q 0 D CLK Q !Q Note that Q follows D when the clock in high, and."— Presentation transcript:

1 Flip-Flops Section 4.3 Mano & Kime

2 D Latch Q !Q CLK D !S !R S R 0 1 1 1 1 0 X 0 Q 0 !Q 0 D CLK Q !Q Note that Q follows D when the clock in high, and is latched when the clock goes to zero.

3 D Flip-Flop 0 1 1 1 1 0 X 0 Q 0 !Q 0 D NCK Q !Q Q !Q D !S !R S R CLK Pulse-narrowing circuit NCK 0 0 1 1 1 0 X 0 Q 0 !Q 0 D CLK Q !Q

4 Pulse-Narrowing Circuit

5 D Flip-Flop CLK DQ !Q 0 0 1 1 1 0 X 0 Q 0 !Q 0 D CLK Q !Q D gets latched to Q on the rising edge of the clock. Positive edge triggered

6 D Flip-Flop CLK DQ !Q y CLK z pulse width setup time hold time propagation delay

7 Making a positive edge-triggered D Flip-Flop from Master-Slave D Latches CLK xzy D E QD E Q CLK’ inputoutput x y z CLK’ CLK masterslave

8 SR Master-Slave Flip-Flop S R CLK Q !Q 0 0 1 Q 0 !Q 0 Store 0 1 1 0 1 Reset 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q 0 !Q 0 Store

9 CLK K Q !Q J J-K Flip-Flop J K CLK Q !Q 0 0 Q 0 !Q 0 0 1 1 0 1 1 Toggle X X 0 Q 0 !Q 0

10 Master-Slave J-K Flip-Flop

11

12 D-Type Positive Edge-Triggered Flip-Flop

13 Positive Edge-Triggered J-K Flip-Flop

14

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