1. Prof. Joongho Choi CMOS CLOCK-RELATED CIRCUIT DESIGN Integrated Circuits Spring 2001 Dept. of ECE University of Seoul

2. Prof. Joongho Choi Non-Overlapping 2-Phase Clocks 1 Using sequential circuits (e.g. counters) & some logics,  1 &  2 can be generated from  0. for Accurate Control of Timing Schemes  for High-Speed Clocks

3. Prof. Joongho Choi Non-Overlapping 2-Phase Clocks 2

4. Prof. Joongho Choi Clock Signal Distribution

5. Prof. Joongho Choi Driving Large Load Capacitance 1 Method 1 : Single Buffer Method 2 : Cascade of Buffers Better Choice How Many Stages & Scaling?

6. Prof. Joongho Choi Driving Large Load Capacitance 2 Inverter Delay 1 Inverter Delay 2 Inverter Delay 3

7. Prof. Joongho Choi Driving Large Load Capacitance 3 Chain of Inverters

8. Prof. Joongho Choi Driving Large Load Capacitance 4 In order to Achieve Minimum Delay For Example, C d =0   =e=2.718 For Example, C d =5fF, C g =10fF, C L =50pF  7 inverters to be cascaded w/ increasing size scaling of 3.18