1. S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 22: Sequential Circuit Design (1/2) Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey/Pearson]

2. S. Reda EN160 SP’08 Sequential circuits Purpose of time: we need time to order events Combinational logic –output depends on current inputs Sequential logic –events are ordered using the clock signal –output depends on current and previous inputs –memory elements are used to store the results of the events or states (certainly if they will be used in the future).

3. S. Reda EN160 SP’08 Differences between latches and flipflops Latches are level sensitive Flipflops are edge triggered

4. S. Reda EN160 SP’08 Basic latch and bistability requirement

5. S. Reda EN160 SP’08 1. Latch Design Pass Transistor Latch Pros +Tiny +Low clock load Cons –V t drop –nonrestoring –output noise sensitivity –dynamic –diffusion input Pass Transistor Latch Pros + Cons

6. S. Reda EN160 SP’08 1. Latch Design Transmission gate + - Transmission gate +No V t drop - Requires inverted clock Inverting buffer + + Fixes either – Inverting buffer +Restoring + Fixes either Output noise sensitivity Or diffusion input –Inverted output

7. S. Reda EN160 SP’08 1. Latch Design Tristate feedback + – Tristate feedback +Static –Output noise sensitivity –Diffusion input Static latches are now essential Buffered input +Fixes diffusion input +Noninverting - Output noise sensitivity

8. S. Reda EN160 SP’08 1. Latch Design Buffered output +Output noise sensitivity eliminated Widely used in standard cells + Very robust (most important) -Rather large -Rather slow (1.5 – 2 FO4 delays) -High clock loading Datapath latch +Smaller, faster - unbuffered input

9. S. Reda EN160 SP’08 2. Flip-flop design Flip-flop is built as pair of back-to-back latches

10. S. Reda EN160 SP’08 2. Latch/Flip-flop with ENABLE Enable: ignore clock when en = 0 –Mux: increase latch D-Q delay –Clock Gating: increase in setup time, skew

11. S. Reda EN160 SP’08 2. Latch/Flip-flop with SET/RESET Set forces output high when enabled Flip-flop with asynchronous set and reset [Figure from Baker]

12. S. Reda EN160 SP’08 Setup and hold times t CLK t D t c 2 q t hold t su t Q DATA STABLE DATA STABLE Register CLK DQ Setup time: the minimum time that the data input must be valid before clock transition Hold time: the minimum time that the data input must be valid after the clock transition

13. S. Reda EN160 SP’08 Sequencing timing terminology t pd Logic Prop. Delay t pdq Latch D-Q Prop Delay t cd Logic Cont. Delay t pcq Latch D-Q Cont. Delay t pcq Latch/Flop Clk-Q Prop Delay t setup Latch/Flop Setup Time t ccq Latch/Flop Clk-Q Cont. Delay t hold Latch/Flop Hold Time