1. ECE 301 – Digital Electronics Brief introduction to Sequential Circuits and Latches (Lecture #14)

2. ECE 301 - Digital Electronics2 Sequential Logic Circuits

3. ECE 301 - Digital Electronics3 Sequential Logic Circuits Combinational Logic Circuits  Output is a function of the inputs only.  Do not have “history” Sequential Logic Circuits  Output is a function of the inputs and the present state.  Have “history”  Maintain state information  Require memory elements

4. ECE 301 - Digital Electronics4 Sequential Logic Circuits

5. ECE 301 - Digital Electronics5 Basic Memory Elements

6. ECE 301 - Digital Electronics6 Basic Memory Elements Latch  Clock input is level sensitive.  Output can change multiple times during a clock cycle.  Output changes while clock is active. Flip Flop  Clock input is edge sensitive.  Output can change only once during a clock cycle.  Output changes on clock transition.

7. ECE 301 - Digital Electronics7 Basic Memory Elements Both latches and flip flops use feedback to achieve “memory”.

8. ECE 301 - Digital Electronics8 A Simple Memory Element AB (what is the problem with this circuit?)

9. ECE 301 - Digital Electronics9 SR Latch (NOR gate implementation)

10. ECE 301 - Digital Electronics10 SR Latch QaQa QbQb QbQb QaQa

11. ECE 301 - Digital Electronics11 Resetting the SR Latch (Qa = 0) SR Latch

12. ECE 301 - Digital Electronics12 SR Latch: S = 0, R = 1 R = 1 → Qa = 0 S = 0 & Qa = 0 → Qb = 1 Latch is reset. Time 1 0 1 0 1 0 1 0 R S Q a Q b ? ? t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 S = 0, R = 1 Qa = 0 Qb = 1

13. ECE 301 - Digital Electronics13 Setting the SR Latch (Qa = 1) SR Latch

14. ECE 301 - Digital Electronics14 SR Latch: S = 1, R = 0 S = 1 → Qb = 0 R = 0 & Qb = 0 → Qa = 1 Latch is set. Time 1 0 1 0 1 0 1 0 R S Q a Q b ? ? t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 S = 1, R = 0 Qa = 1 Qb = 0

15. ECE 301 - Digital Electronics15 Storing the value in the SR Latch (Qa + = Qa) SR Latch

16. ECE 301 - Digital Electronics16 SR Latch: S = 0, R = 0; Qa = 0 S = 0 & Qa = 0 → Qb = 1 R = 0 & Qb = 1 → Qa = 0 Behavior of latch is consistent. Time 1 0 1 0 1 0 1 0 R S Q a Q b ? ? t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 S = 0, R = 0 Qa = 0Qb = 1 Qa = 0 Latch stores the value of Qa

17. ECE 301 - Digital Electronics17 SR Latch: S = 0, R = 0; Qa = 1 S = 0 & Qa = 1 → Qb = 0 R = 0 & Qb = 0 → Qa = 1 Behavior of latch is consistent. Time 1 0 1 0 1 0 1 0 R S Q a Q b ? ? t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 S = 0, R = 0 Qa = 1 Qb = 0 Qa = 1 Latch stores the value of Qa

18. ECE 301 - Digital Electronics18 The undefined state of the SR Latch (Qa = Qb = 0) SR Latch

19. ECE 301 - Digital Electronics19 SR Latch: S = 1, R = 1 S = 1 → Qb = 0; R = 1 → Qa = 0 Time 1 0 1 0 1 0 1 0 R S Q a Q b ? ? t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 S = 1, R = 1 Qa = 0 Qb = 0

20. ECE 301 - Digital Electronics20 SR Latch: S = 1, R = 1 S = 1 → Qb = 0; R = 1 → Qa = 0 Time 1 0 1 0 1 0 1 0 R S Q a Q b ? ? t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 S = 1, R = 1 Qa = 0 Qb = 0

21. ECE 301 - Digital Electronics21 SR Latch: The undefined state What if both S and R transition from 1 to 0 at the same time? (S = 1 → 0 & R = 1 → 0)

22. ECE 301 - Digital Electronics22 SR Latch: The undefined state If S and R both transition to 0 simultaneously,  Output is unpredictable  Dependent on speed of the 2 NOR gates. Time 1 0 1 0 1 0 1 0 R S Q a Q b ? ? t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 S = 1 → 0 R = 1 → 0 Qa = ? Qb = ?

23. ECE 301 - Digital Electronics23 SR Latch: The undefined state If the top NOR gate is faster,  then R = 0 & Qb = 0 → Qa = 1  and then S = 0 & Qa = 1 → Qb = 0.  Stores Qa = 1, Qb = 0 (set). Q a Q b R S

24. ECE 301 - Digital Electronics24 SR Latch: The undefined state If the bottom NOR gate is faster,  then S = 0 & Qa = 0 → Qb = 1  and then R = 0 & Qb = 1 → Qa = 0.  Stores Qa = 0, Qb = 1 (reset). Q a Q b R S

25. ECE 301 - Digital Electronics25 SR Latch (NAND gate implementation)

26. ECE 301 - Digital Electronics26 SR Latch

27. ECE 301 - Digital Electronics27 Gated SR Latch (NAND Gate Implementation)

28. ECE 301 - Digital Electronics28 Gated SR Latch S' R'

29. ECE 301 - Digital Electronics29 Gated SR Latch: State Equation State Equation: Q + = S + R'.Q  Q is the present (or current) state.  Q + is the next state. After the transition of the output Q.  The next state is a function of the inputs and the present state. Inputs: S and R Present State: Q  Note: Q is also denoted as Q(t)  and Q + is also denoted as Q(t+1).

30. ECE 301 - Digital Electronics30 Gated D Latch

31. ECE 301 - Digital Electronics31 Gated D Latch S' R' S R

32. ECE 301 - Digital Electronics32 Gated D Latch: Clk = 0 Clk = 0 Clk = 0 → S' = R' = 1 S' = R' = 1 → Q + = Q  Next state = present state Latch stores the value of Q

33. ECE 301 - Digital Electronics33 Gated D Latch: Clk = 1 Clk = 1 Clk = 1 → S' = D', R' = D S' = D', R' = D → Q + = D  Next state = input Output (Q) follows the input (D)

34. ECE 301 - Digital Electronics34 Gated D Latch State Equation: Q + = D  Q + is the next state  D is the input Eliminates the unstable case  S' = R' = 0 cannot occur. S' = R' = 0 is the same as S = R = 1.  The values of S' and R' are always complementary when the clock is high (active).

35. ECE 301 - Digital Electronics35 Gated D Latch: Issues Must satisfy setup and hold times.  Otherwise, the output will be unpredictable or metastable. Glitches on D are passed to Q when clock is high.  Use edge-triggered or Master-Slave D Flip-Flop to overcome this undesirable behavior. t su t h Clk D Q

36. ECE 301 - Digital Electronics36 Latches: Symbols QQ Q

37. ECE 301 - Digital Electronics37 Acknowledgments The slides used in this lecture were taken, with permission, from those provided by Pearson Prentice Hall for Digital Design (4 th Edition). They are the property of and are copyrighted by Pearson Education.