1. DIGITAL LOGIC CIRCUITS 20111875 조수경 2012-09-151DIGITAL LOGIC CIRCUITS

2. CONTENTS 1.BASIC LOGIC BLOCK 2.FILP-FLOPS(F/F) 3.DIFFERENCE OF LATCH & F/F 4.Master-Slave F/F 5.CLOCK PERIOD 6.SEQUENTIAL CIRCUITS 1.REGISTERS 2.COUNTERS * LOGIC CIRCUIT DESIGN EXAMPLE 2012-09-152DIGITAL LOGIC CIRCUITS

3. BASIC LOGIC BLOCK Combinational Logic Block –Output value decided by the current input value. –There is no memory cell. –MUX, Encoder, Decoder, Parity Checker, Parity Generator, etc. Sequential Logic Block –Output value decided by 2 values. The current input value and state value of the block. –There is memory cell. –F/F Memory cell’s feedback line 2012-09-153DIGITAL LOGIC CIRCUITS

4. CLOCKED F/F 2012-09-154DIGITAL LOGIC CIRCUITS

5. LATCH? FLIP FLOPS? Latches Positive Edge-triggered F/F 2012-09-155DIGITAL LOGIC CIRCUITS

6. Master-Slave F/F Act when CP is rising or falling. Master slave JK F/F is prevent about race around. SR2 Inactive SR1 Active SR2 Active SR1 Inactive SR2 Inactive SR1 Active SR1 SR 2 2012-09-156DIGITAL LOGIC CIRCUITS

7. SR2 Inactive SR1 Active SR2 Active SR1 Inactive SR2 Inactive SR1 Active SR1 SR 2 2012-09-157DIGITAL LOGIC CIRCUITS

8. Clock Period CLOCK PERIOD T = CPU 속도의 역수 = t d + t s + t h Setup timeHold time 2012-09-158DIGITAL LOGIC CIRCUITS

9. Sequential Circuits - Register 2012-09-159DIGITAL LOGIC CIRCUITS

10. Sequential Circuits - Counter 2012-09-1510DIGITAL LOGIC CIRCUITS

11. LOGIC CURCUIT DESIGN EXAMPLE 2012-09-1511DIGITAL LOGIC CIRCUITS

12. THANK YOU 2012-09-1512DIGITAL LOGIC CIRCUITS