1. CEC 220 Digital Circuit Design Latches and Flip-Flops Monday, March 03 CEC 220 Digital Circuit Design Slide 1 of 19

2. Lecture Outline Monday, March 03 CEC 220 Digital Circuit Design Latches Flip-Flops Slide 2 of 19

3. Latches and Flip-Flops Monday, March 03 CEC 220 Digital Circuit Design Up until this point – Combinational Logic  No memory Now we will consider – Sequential circuits  Circuits with memory  Typically, this is accomplished via feedback!! Slide 3 of 19

4. Latches and Flip-Flops Monday, March 03 CEC 220 Digital Circuit Design A simple feedback circuit (inverter with a delay) Slide 4 of 19

5. Latches and Flip-Flops Monday, March 03 CEC 220 Digital Circuit Design An Inverter with Stable Feedback  Assume 10 ns gate delays Time = 0 ns 0??1 Time = 10 ns 0 Time = 20 ns Circuit retains the values  Has memory Slide 5 of 19

6. Latches and Flip-Flops Monday, March 03 CEC 220 Digital Circuit Design An Inverter with Stable Feedback  Assume 10 ns gate delays Time = 0 ns 1??0 Time = 10 ns 1 Time = 20 ns Circuit retains the values  Has memory Slide 6 of 19

7. Latches and Flip-Flops Monday, March 03 CEC 220 Digital Circuit Design Consider the NOR-NOR circuit  Assume 10 ns gate delays AB 001 010 100 110 0 0 S R Q 1 0 0 Slide 7 of 19

8. Latches and Flip-Flops The S-R Latch Monday, March 03 CEC 220 Digital Circuit Design = 05001000 R S Q Q’Q’ 0 1 0 0 ResetSetHold SetForbidden Slide 8 of 19

9. Latches and Flip-Flops The S-R Latch Monday, March 03 CEC 220 Digital Circuit Design Behavior of the S-R Latch: S-R Latch R S SRQ 00Hold 01Reset 10Set 11Not Allowed Slide 9 of 19

10. Latches and Flip-Flops The S-R Latch Monday, March 03 CEC 220 Digital Circuit Design The “Next-State” or “State Transition” Chart S(t)R(t)Q(t) Q(t+  t) 000 001 010 011 100 101 110 111 QUESTION: What is the “state” of the latch? QUESTION: What is the “state” of the latch? ANSWER: The “state” of the latch refers to the value of the output. ANSWER: The “state” of the latch refers to the value of the output. The current output depends on past output – the circuit has memory!! 0 1 0 0 1 1 X X Hold Reset Set Not Allowed InputsStateNext State Slide 10 of 19

11. Latches and Flip-Flops The S-R Latch Monday, March 03 CEC 220 Digital Circuit Design What is the logic expression for the “Next State” ?  Use a K-map!! S(t) R(t)Q(t) 01 0001 0111 110X 100X Q(t+  t) Slide 11 of 19

12. Latches and Flip-Flops The S-R Latch Monday, March 03 CEC 220 Digital Circuit Design An application of the S-R Latch  Debouncing a mechanical switch Slide 12 of 19

13. Latches and Flip-Flops The Gated Latch Monday, March 03 CEC 220 Digital Circuit Design The Gated D-Latch  Solve the S=1 & R=1 not allowed issue!!  Now we have a D-Latch S-R Latch S R S=1 & R=1 can NOT occur!! D 1 1 0 0 0 1 The D-Latch: Q simply follows D The D-Latch: Q simply follows D Slide 13 of 19

14. Latches and Flip-Flops The Gated Latch Monday, March 03 CEC 220 Digital Circuit Design The Gated D-Latch  Now “Gate” the inputs S-R Latch S R D G S = 0 & R = 0 (hold) Slide 14 of 19

15. Latches and Flip-Flops VHDL Code for Gated D-Latch Monday, March 03 CEC 220 Digital Circuit Design entity GDL is port( D, G : in bit; -- D is the Data input & G is the gate input Q, QN: out bit); -- Q and QNot are the outputs end GDL; architecture GDL_eqns of GDL is signal S,R, Qinternal: bit; begin S <= D and G after 5 ns; R <= not D and G after 5 ns; Qinternal <= '1' when S = '1' and R = '0' else '0' when S = '0' and R = '1'; -- S&R = “11” is not allowed -- S&R = “00” is the hold state Q <= Qinternal after 10 ns; QN <= not Qinternal; End GDL_eqns; Run The Simulation Run The Simulation Slide 15 of 19

16. Latches and Flip-Flops Flip-Flops Monday, March 03 CEC 220 Digital Circuit Design Edge-Triggered devices  The D Flip-Flop Slide 16 of 19

17. Latches and Flip-Flops Timing Diagram Monday, March 03 CEC 220 Digital Circuit Design D Clk Q rise Q fall 100 Q Gated latch Rising edge triggered D FF Falling edge triggered D FF 50 Gated D Latch Slide 17 of 19 Assume that all Q’s starts at ‘0’ G=

18. Latches and Flip-Flops Monday, March 03 CEC 220 Digital Circuit Design Setup and Hold Time Setup Time (Tsu) Clock: Periodic Event, causes state of memory element to change rising edge, falling edge, high level, low level There is a timing "window" around the clocking event during which the input must remain stable There is a timing "window" around the clocking event during which the input must remain stable Minimum time before the clocking event by which the input must be stable Hold Time (Th) Minimum time after the clocking event during which the input must remain stable Slide 18 of 19

19. Next Lecture Monday, March 03 CEC 220 Digital Circuit Design D Flip-Flop review VHDL code for a D Flip-Flop S-R, J-K, T Flip-Flops Registers Slide 19 of 19