1. Dept. of Electrical Engineering
Digital Logic Design (41-135) Chapter 7 Flip-flops, Registers, Counters, and a Simple Processor
Younglok Kim
Dept. of Electrical Engineering
Sogang University
Spring 2006

2. Chapter Objectives Logic circuits that can store information
Flip-flops, which store a single bit
Registers, which store multiple bits
Shift registers, which shift the contents of the register

3. Sequential vs. Combinational Circuits
Up to now, we learned combinational circuits.
Sequential circuits
Includes storage/memory elements
State: contents of the storage element
Changes through a sequence of states

4. Mechanism of State ChangeB
Simple memory element
Controlled memory element A B
Output
Data
Load
TG1
TG2

5. Types of Storage Elements
Latchs
Basic latch
Gated SR latch
Gated D latch
Flip-flops
Master-slave D flip-flop
Edge-triggered D flip-flop
T flip-flop
JK flip-flop

6. Basic Latch
Cross-coupled NOR gates

7. Application of Latch Control of alarm system
For enable/disable option, use gated latch
Memory
element
Alarm
Sensor
Reset
Set On
Off

8. Gated SR Latch

9. Gated SR Latch with NAND
Exactly same operation with the previous one
Smaller number of TRs rather than previous realization S R
Clk Q

10. Gated D Latch

11. Effect of Propagation Delays
Setup time (about 3 ns)
Hold time (about 2 ns) t su t h
Clk D Q

12. Master-Slave D Flip-Flop
Graphical symbol
Structure of M-S D FF (built with 2 latches)
Negative edge triggered

13. Positive Edge-Triggered D Flip-Flop
Setup time = delay of G4 & G1
from D to P3
Hold time = delay of G3
from clock to P2

14. Level-Sensitive vs. Edge-Triggered

15. M-S D FF with Clear & Preset

16. Positive-Edge Triggered D FF with Clear & Preset

17. Asynchronous vs. Synchronous Clear
Asynchronous clear
Make Q=0 immediately, regardless of value of clock signal.
Synchronous clear

18. T Flip-Flop (Toggle)

19. JK Flip-Flop