1. NOTICES
Final Homework 4.10, 4.13, 4.14, 4.18 Due Monday March 15 Before 12:00 Noon (EECS Mailbox)
Final Project Report due by Monday March 15

2. NOTICES
Online Lectures and Quiz Solutions
Check Grade Page
Homework

3. NOTICES Congratulations on completing Final Project!
Publish your work!
Resume/Job Applications
Mentor Graphics
EE416
Thank You!

4. Final Exam Tuesday March 16 at 8:00 AM in Rm. 317
Comprehensive (focus on latter part)
Open Book, Notes, Quizzes, Homework, Lectures
Open ended questions
Bring color pencils
Go though Quizzes and Homework
Probably 4 questions (may have a choice)

5. SEQUENTIAL LOGIC
Read Chapter 6

6. Master-Slave Flip-Flop

7. 2 phase non-overlapping clocks

8. 2-phase dynamic flip-flop

9. Flip-flop insensitive to clock overlap
Two Modes
Evaluation
Hold

10. How does C2MOS work?
Operates as a negative edge-triggered master-slave D FF 
Two Modes
Evaluation
Hold
 = 1 
In  CL1
 = 0 
CL1  CL2

11. Flip-flop insensitive to clock overlap
Two Modes
Evaluation
Hold

12. C2MOS avoids Race Conditions
condition for signal propagation  active PDN followed by active PUN D In 1 M 3 2 6 7 5 V DD
(a) (1-1) overlap X
only PDN are enabled  input cannot propagate to output

13. C2MOS avoids Race Conditions
condition for signal propagation  active PUN followed by active PDN D In V DD M 1 4 2 6 8 5
(b) (0-0) overlap X
only PUN are enabled  input cannot propagate to output

14. Pipelining

15. Pipelined Logic using C2MOS

16. Example
i.e. logic functions (implemented using static CMOS) between latches must be non-inverting

17. NORA CMOS Stands for NO-RAce CMOS
Implements fast pipelined datapaths using dynamic logic
Combines C2MOS pipeline registers and np-CMOS dynamic logic blocks
Module consists of a comb. logic block (static, dynamic, or mixed) followed by a C2MOS latch
Logic and latch are clocked so that both are in evaluation or hold (precharge) mode simultaneously
Block which is in evaluation during  = 1 is called a -module
NORA datapath consists of alternating blocks on  and _BAR modules

18. NORA CMOS Modules

19. Design Rules for NORA CMOS
The dynamic logic Rule:
Inputs to a dynamic n (p) block are only allowed to make a 0  1 (1  0) transition during the evaluation period
The C2MOS Rule:
The number of static inversions between C2MOS latches should be even (in the absence of dynamic nodes); if dynamic nodes are present, the number of static inverters between a latch and a dynamic gate in the logic block should be even. The number of static inversions between the last dynamic gate in a logic block and the latch should be even as well.

20. NORA CMOS Modules