1. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic SEQUENTIAL LOGIC

2. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic

3. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Positive Feedback: Bi-Stability Input and Output Roles are changed.

4. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Meta-Stability V i 2 = V o 1 V i1 = V o2 C V i 2 = V o 1 V i1 = V o2 B  Gain should be larger than 1 in the transition region

5. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic SR-Flip Flop Q S R Q S R Q Q 1 0 1 0 1 1 0 0 Q 1 0 1 Q 0 1 1 Q Q Forbidden states Can be used for non- Overlapping clocks

6. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic JK- Flip Flop Eliminates the forbidden state. Called a latch because the gate is transparent when clock is high NAND

7. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Other Flip-Flops

8. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Race Problem To avoid, use a master-slave FF

9. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Master-Slave Flip-Flop J K  MASTER SLAVE Q J K Q  PRESET CLEAR SI RI High  Low 

10. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Propagation Delay Based Edge-Triggered Output only pulses for a short time

11. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Edge Triggered Flip-Flop

12. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Flip-Flop: Timing Definitions

13. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Maximum Clock Frequency Propagation delay in the longest path in comb. logic Clock period

14. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic CMOS Clocked SR- FlipFlop Similar to Dual Cascade Voltage Switch Logic (DCVSL) Q =  S + Q Q =  R + Q

15. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic CMOS Clocked SR- FlipFlop Q Q R S  M1 M3 M4M2 M6 M5M7 M8 =1 =0 We want to set this FF What should the sizes be for VLT = Vdd/2? Notice that M2 = On and M1 = Off At VLT  M2, M6, M5 = Sat Assume M6 = M5   n = 1/2  (6,5) Solve:

16. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Flip-Flop: Transistor Sizing Vr M5, M6, M7, M8 M2 = M4 = 5.4u/1.2u M1 = M3 = 1.8u/1.2u

17. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic 6 Transistor CMOS SR-Flip Flop

18. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Charge-Based Storage

19. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Master-Slave Flip-Flop

20. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic 2 phase non-overlapping clocks

21. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic 2-phase dynamic flip-flop

22. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Flip-flop insensitive to clock overlap

23. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic C 2 MOS avoids Race Conditions

24. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Pipelining

25. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Pipelining

26. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Pipelined Logic using C 2 MOS C 2 C 1 G C 3 NORA CMOS What are the constraints on F and G? F and G MUST be non-inverting NO RAce Logic 

27. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Example Number of a static inversions PER STAGE should be even

28. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic NORA- np CMOS Modules Alternate Types of Logic

29. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Doubled C 2 MOS Latches Doubled p-C2MOS Latch Mixed are used for a pipeline chain. Only one clock is used.

30. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic TSPC - True Single Phase Clock Logic

31. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Schmitt Trigger VTC with hysteresis Restores signal slopes

32. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Noise Suppression using Schmitt Trigger

33. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic CMOS Schmitt Trigger Moves switching threshold of first inverter

34. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Schmitt Trigger Simulated VTC

35. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic CMOS Schmitt Trigger (2)

36. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Multivibrator Circuits

37. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Transition-Triggered Monostable

38. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Monostable Trigger (RC-based)

39. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Astable Multivibrators (Oscillators)

40. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Voltage Controller Oscillator (VCO)

41. Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Relaxation Oscillator Out 2 CR 1 Int I1 I2