® Xilinx XC9500 CPLDs. ® www.xilinx.com  High performance —t PD = 5ns, f SYS = 178MHz  36 to 288 macrocell densities  Lowest price, best value CPLD.

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Presentation transcript:

® Xilinx XC9500 CPLDs

®  High performance —t PD = 5ns, f SYS = 178MHz  36 to 288 macrocell densities  Lowest price, best value CPLD  Highest programming reliability  Most complete IEEE JTAG  Space-efficient packaging, including chip scale pkg XC MHz XC9500XL 200MHz XC9500XL Key Features Lowest Price Per Macrocell

® XC9500XL/XV Architecture Embraces In-System Changes  Advanced, 2nd Generation Pin-Locking —Superior routability with speed  Maximum Flexibility —54-input function block fan-in —90 p-terms per output —3 global, locally invertible clocks —Global set/reset pin —P-term OE per macrocell —Clock enable

® XC9500XL/XV System Features  I/O Flexibility —XL:5v tolerant; direct interface to 3.3v & 2.5v —XV:5v tolerant; direct interface to 3.3v, 2.5v & 1.8V  Input hysteresis on all pins  User programmable grounds  Bus hold circuitry for simple bus interface  Easy ATE integration for ISP & JTAG —Fast, concurrent programming times

® XC9500XL/XV Family 3.3v ISPXC9536XLXC9572XLXC95144XLXC95288XL 2.5v ISPXC9536XVXC9572XVXC95144XVXC95288XV Macrocells Usable Gates t pd (ns) XC9500XL t pd (ns) XC9500XV 4556 Registers f SYSTEM XC9500XL XC9500XV Packages PC44 CS48 VQ44* VQ64 TQ100 TQ144 CS144PQ208 BG256 FG256* CS280* * available in 2Q00

® XC9500 5V Family XC9536 Macrocells Usable Gates t PD (ns) Registers Max. User I/Os Packages 44VQ 44PC 48CSP 44PC 84PC 100TQ 100PQ 84PC 100TQ 100PQ 160PQ 100TQ 100PQ 160PQ HQ 352BG 160PQ 208HQ 352BG XC9572XC95108XC95144XC95216XC /97

® Most Complete JTAG Testability  IEEE Std boundary-scan —Testability & advanced system debug/diagnosis —8 instructions supported (incl. CLAMP)  Full support on all family members  Industry-standard ISP interface  Complete 3rd party support

® FLASH Technology Enables Rapid Die Size Reduction 1.0x 0.3x 0.2x 0.5x 0.6u/2LM0.5u/3LM0.35u/4LM0.25u/4LM µ = 0.5µ transistor with 0.35µ interconnect 5V 3.3V 0.12x 0.18u/5LM V 0.3x 2.5V DELIVERED On schedule DELIVERED 2000

® Xilinx CPLD Process Leadership Non-Volatile TechnologyMemories Year used in SPLD/CPLD Pioneer Year used in Bipolar Fuse MMI (AMD) EPROM V EEPROM V FLASH V FLASH Altera EP-series Lattice ispLSI Xilinx XC9500 Xilinx XC9500XL 2.5V FLASH Xilinx XC9500XV

® Web-Powered CPLD Software Integrated CPLD Design Environment —FREE, downloadable solution —VHDL, Verilog & ABEL synthesis —Modular, efficient CPLD design On-line CPLD Design Analysis —Accepts any input —Complete XC9500 Series evaluation —On-line pricing, saves money

® Xilinx CPLDs Performance ISP Price Lowest, best value Ultra Low Power CoolRunner Reliability 10,000 program/erase cycles 20 year data retention Technology True, 0.35u Flash Pin-Locking Industry’s Best Density 12% More M/Cs 22V10s to 960 M/Cs JTAG Family Support Packaging TQ/PQ & 0.8mm CSP Silicon Xpresso WebFITTER WebPACK Speed Fast t PD, f SYS

® Appendix Slides to Follow

® Xilinx Programmable Logic Solutions System Gates XC9500 CPLDs - XC9500XL (3.3v) - XC9500 (5v) - XC9500XV (2.5v) Key Features - 36 to 288 macrocells - High performance - Low cost - In-system programmable - Chip scale packages Spartan FPGAs - SpartanXL (3.3v) - Spartan (5v) Key Features - Low cost ASIC replacement - 5K to 40K system gates - High performance - SelectRAM memory - Chip Scale packages Features 5K1K40K

® Supports high-growth market segments: Communications, Computers, Consumer New 48-pin CSP: 1/3 size of the VQ44 Uses standard IR techniques for mounting to PC board Chip Scale Packaging Leadership