Introduction to Xilinx CPLDs

Introduction to Xilinx CPLDs

Agenda CPLD Introduction XC9500 Family Overview
CoolRunner XPLA3 Overview CoolRunner-II Overview IQ Products for Automotive and Industrial Software Updates and Online Support Customer Success Stories

Complex Programmable Logic Device
macrocells interconnect macrocells The “Digital Logic Device” category contains 7 types of devices: standard logic (a.k.a. TTL), simple Programmable Logic Devices (PLD), Complex Programmable Logic Devices (CPLD), Field Programmable Gate Array (FPGA), Gate Array, Standard Cell and Full Custom. This training module is focusing on CPLDs with current annual sales approaching one billion dollars and with cumulative average growth rate of 32% until at least the year 2000! CPLDs consist of relatively few PLD blocks or “macrocells” on a single device with general purpose interconnect in between. The combination of many AND gates feeding a few OR gates is often referred to as “sum-of-products” . Simple design sections can be implemented within a single block. More sophisticated logic will require multiple blocks and use the general purpose interconnect in between to make these connections. A hybrid of PLD blocks & interconnect for mid-size logic designs

CPLD Design Flow Gates of the design ... CPLD Design Flow
Specification libraries HDL Schematic Capture Synthesis netlist Gates of the design ... CPLD Design Flow Verification Simulation test vectors Implementation Translate Timing Analyzer Back-Annotation Fitting ... are “fitted” to the CPLD As we saw in Module 2, designing a CPLD requires 4 basic steps: specification, verification, implementation and system debug. During Specification the function of the design is entered using a schematic (graphical), simple equations (text-based e.g. ABEL) or high level description (text-based e.g. VHDL). Verification is the process of determining if the circuit works as desired using a simulator. After all problems have been fixed, it’s time to turn the netlist (computer description of the design) into a programmed device. Fitting is the most important part of design Implementation. Very clever software is used to “Fit” the design to the target device in order to use the available gates, flip-flops, interconnect and I/Os in the best possible way. In the diagram above, a section of the design is “fit” to the CPLD. The biggest potential problem during fitting occurs if the designer has previously assigned the exact locations of the I/O pins, commonly referred to as Pin Locking. (Most often this is from a previous design iteration and has now been committed to the printed circuit board layout). Architectures (like the Xilinx XC9500/XL) that support I/O pin locking have a very big advantage. They permit the designer to keep the original I/O pin placements regardless of the number of design changes, utilization or required performance. Download/ Program device System Debug printed circuitboard

High Performance Pin-to-Pin combinatorial delay
Time from input, thru interconnect to output (ns) Maximum registered frequency Fastest operation of flip-flops (MHz) CPLD TPD (ns) CPLD Macrocell When it comes to performance, CPLD designers are primarily concerned about 2 numbers: pin-to-pin delay and the maximum frequency. Pin-to-pin delay is simply the time it takes to get from an input pin, thru the gates of a single macrocell and to an output pin. This critical parameter is measured in nanoseconds (ns) - one billionth of a second. Maximum Frequency is the fastest rate that the flip-flops on the device can be run. The clock pin is typically connected to all the flip-flops in the device. The maximum frequency is measured in megahertz (MHz) - one million cycles per second. ( fMAX (MHz)

Wide Package Offering High pin count package for lots of I/Os
Maximum logic with minimal I/Os Logic consolidation for space (vs. discrete devices) Lower cost packaging A smaller CPLD package means a smaller board! CPLD A wide package selection is very important to CPLD designers. They may need a large package with a high pin count because of the many user I/Os required in the design. Conversely, they may have very few user I/Os and want the smallest possible package to reduce board space. A smaller board means lower costs: less PCB material, shorter manufacturing time, easier handling and cheaper shipping. A particular type of package may be specified (e.g. Ball Grid Array) to be compatible with the manufacturing flow. Or the designer simply wants the cheapest package possible. CPLD

CPLD Voltage Integration 5v, 3.3v, 2.5v, 1.8v and 1.5v
3.3v & 2.5v is the current market trend moving to 1.8v and below for portable and low power applications Cost reduction to eliminate 5v supply and regulators with 5v tolerance Some components will not migrate to 3.3v or below Need to interface with 3.3v, 2.5V, 1,8v and/or 1.5v components CPLD 3.3/2.5/1.8v 5v* 5v* 5v* 5v* 5v* Supply voltage for CPLDs has been traditionally 5 volts. With the 3.3 volt market trend now well underway, designers are starting to require 3.3v CPLDs to keep up with the micro and memory chips that have made this transition. The smallest integrated circuit geometry (below 0.35 micron) force the lower voltage levels. A big boon to designers is the ability to replace the 5 volt supply with a cheaper 3.3v one. Designers however have to deal with the reality that not all components have 3.3v counterparts and so must be able to handle a mixture of both. This means that the CPLD needs to meet this challenge without additional components. In some cases, components will not be migrated to 3.3v because of physical limitations or financial ones. Clearly, a opportunity to integrate the logic of this obsolete device into a CPLD. 3.3v* 1.5v* 1.8v* 2.5v* * 3.3v CPLD required to interface with 5v, 3.3v & 2.5v components * 2.5v CPLD required to interface with 3.3v, 2.5v & 1.8v components *1.8v CPLD required to interface with 3.3v, 2.5v, 1,8v & 1.5v components

System Integration Advantage

System Level Savings High volume economies of scale Reference designs
Single chip for multiple system solutions Increase volume means reduction in all related costs Reference designs Minimize risk and shorten design cycle Lowest cost per I/O Examples include On The Fly (OTF) reconfiguration Two devices for the price of one

Designers Need Low Power
Longer lasting battery life Lower overall system cost (eliminate fans/ reduce power supplies) Increased system reliability Fits into hand-held applications Low power is the dominant designer requirement for some applications. The obvious benefit of low power is longer battery life. But low power also means lower overall system cost since smaller power supplies with smaller or no cooling fans/heat sinks can be used. In some cases, the application can be completely sealed. Lower temperature means increased reliability, also a good thing. And low power can allow hand-held applications due to reduction in the system size.

CPLD Advantage over Discrete Logic
High Speed CMOS Logic 74HC373 74HC137 74HC374 74HC138 74HC157 74HC00 74HC20 74HC21 TSSOP 24 SOL 24 XPLATM Architecture Equivalent to TQFP 100 XCR3128XL Or XCR3064 XL 3.3V parts in the same package bridging two densities for added design flexibility The integration of 74 series standard logic into a low cost CPLD is a very attractive proposition. Not only do you save PCD area and layers therefore reducing your total system cost but you purchase and stock one generic part instead of upto as many as twenty pre-defined logic devices. In production the pick and place machine only has to place one part - therefore speeding up production. Less parts means higher quality and better FIT factor. In this customer design a Xilinx Coolrunner device was used which is our family of ultra low power parts so the customer benefited from low power consumption and reduced thermal emissions. This lead to the reduction of heat sinks (another cost saving) and a higher reliability end product. Real design example: Aircraft Passenger Handset - Smaller PCB with less layers (lower cost) - 7 to 3 layers! - One part to purchase & stock, less inventory - One part to pick and place in manufacture, saving time - Design can be changed and enhanced without PCB re-layout - even in the field - Stock and purchase one part instead of 17 in this example!

Xilinx CPLD High Volume Shipments
Units Shipped We’re the fastest growing CPLD company in the industry Xilinx currently ships >10M CPLD units per Qtr WW CPLD market share growing at >1% per Qtr

CPLD Product Portfolio
3.3V core 2.7V - 5V I/O LVCMOS, LVTTL Low power Fast Zero Power 1.8V RealDigital core 1.5V - 3.3V I/O SSTL, HSTL, LVCMOS, LVTTL Lower power DataGATE Clocking features Clock Divide CoolCLOCK DualEDGE I/O banking 2.5V core 1.8V - 3.3V I/O LVCMOS, LVTTL I/O banking 3.3V core 2.5V - 5.0V I/O LVCMOS, LVTTL

Quick Design Capability with CPLDs
CoolRunner-II is the only CPLD that combines both high speed and ultra low power operation. With the speed of the 9500XV and lower power performance than XPLA3, this new era of CPLDs will establish itself as the leading edge process technology for future CPLDs from Xilinx. A new class of CPLD from Xilinx with high performance (speed plus advanced feature set) and ultra low power without a price compromise. The best CPLD solution available.

Product Lifetime Dynamics
Units Cellular Target high volume, short production life applications PDA PC Games TV If you look at how quickly new products take to reach a market volume of 1 million units, two trends are noticeable. 1. New products take less time to hit volume this also means that 2. They will more than likely stay there for much shorter periods 1 2 Years in Production New products stay in volume for shorter periods, Time To Market is critical!

ASIC Development Take Too Long!
Product life cycles maybe shorter than ASIC development time Multiple ASIC spins may miss the market window Smaller than expected run rates may not justify the ASIC development cost Long ASIC development times do not allow last minute design revision changes Revisions leave little time to run in production Programmable logic allow customers to address market changes quicker

ASICs Give Designers Only ONE Chance
Freeze design here No chance for last minute design changes ASIC Spec Design & Verification Silicon Prototype System Integration Silicon Production First Ship Re-programming allows last minute design changes CPLD Spec Design & Verification System Integration First Ship Here is a typical ASIC design cycle. There are many different flows and this is just one example. It starts with the specification phase, then design and verification, moving into fabricating a prototype of the ASIC. Then, integration with the software and the rest of the system can begin. Once everything is working, assuming you don’t need a re-spin, you can wait around for production silicon, then finally ship the product. Because of the risk involved in making changes, you must freeze your design (features) during the specification phase. This leaves a very long time between design freeze and first customer ship. The FPGA design cycle take much less time. Specification, design and verification take much less time because of the reduced risk of making mistakes. The specification should be allowed to be more fluid since requirements may change anyway. Verification takes much less time because you can do in system testing and many things don’t need to be verified with exhaustive simulations. Notice how the flexibility of the FPGA design methodology allows you to move the design freeze date to much later in the cycle. This gives you a much better chance of meeting your customers requirements. Freeze design here CPLD flexibility allow performance analysis and late HW/SW changes meeting customer needs and improves Time To Market with faster, lower risk designs

CoolRunner Reference Designs
Shorten design cycle time Eliminate code porting costs for next design cycle Re-use of HDL is reliable and stable Minimize design risk by using reference designs Availability of reference designs prepares you for unexpected system changes Update main processor but it does not incorporate correct bus interface Further improve customer’s Time To Market Proven designs for quick turn requirements

Faster Designs with FREE CoolRunner Reference Designs
Coming soon Free VHDL design code:

CoolRunner-II Design Kit

Development Board & Cable Support
Note: There may be regional variations because of different mains voltages - check locally for full part number

CPLD Software Improvements in 6.1
Ease of use Improved CPLD process flow Single process (Implement Design) will pull the design through the entire fitting process Granular control still possible for power users by expanding individual processes New design creation aids New project wizard leads the user through the project creation process Add existing source / Create new source processes - assist in getting started faster Centralized process properties menu Web Update Built in utility checks for service packs and supplemental CPLD updates Downloads and installs update in single step XC9500XL / XV Product Overview File Number Here

Xilinx CPLD Process Leadership
Year used in Year used in SPLD/CPLD Non-Volatile Technology Memories SPLD/CPLD Pioneer Bipolar Fuse 1973 1978 MMI (AMD) EPROM 1979 1984 Altera EP-series 5V EEPROM 1986 1991 Lattice ispLSI 5V FLASH 1990 1995 Xilinx XC9500 3.3V FLASH 1993 1998 Xilinx XC9500XL 2.5V FLASH 1996 2000 Xilinx XC9500XV

Higher Voltage CPLD Solutions To Fit Every Need
5 / 3.3 / 2.5V core macrocells High Performance Superior pin-locking Low cost XC9500 Families XC9500 XC9500XL XC9500XV 5V core 3.3V core 2.5V core

XC9500/XL/XV Family Features Overview
CPLD Designer Needs High fMAX = 278 MHz Fast TPD = 3.5nS Instant productivity software tools Best pin-locking capability Best ISP/JTAG support Support for all ATE manufacturers Advanced packaging including CSP XC9500XL for 3.3v (5v tolerant & 2.5v I/O) XCR9500XV for 2.5v (1.8v & 3.3v I/O) Best CPLD pricing in the industry! High Performance Time to Market Fit in Existing Flow Package offering 5v,3.3v & 2.5v Lowest cost The Xilinx XC9500 and XC9500XL families meet all the designer CPLD requirements! The two critical performance numbers for the XC9500XL family are very impressive: 200MHz maximum clocking performance and 4 ns pin-to-pin delay. There are few applications indeed that need faster performance. The XC9500 performance is still quite respectable for 5v solutions. The Foundation & Alliance 1.5 software tools offer instant productivity and a very fast learning curve. This with the best pin-locking capability in the industry means fast time to market for designers. Easy ATE integration for ISP & JTAG (industry standard) for fast, concurrent programming times, supporting all ATE vendors. Both families offer a wide range of packages including the Chip Scale Package which Xilinx help pioneer. The XC9500 family is designed for 5 volt systems. The 9500XL is optimized for 3.3v operation while providing compatibility between 5v, 3.3v and 2.5v components. As for low cost, quite simply we have the best pricing in the industry!

XC9500XL / XV Families 3.3v ISP XC9536XL XC9572XL XC95144XL XC95288XL
XC9536XV XC9572XV XC95144XV XC95288XV Macrocells 36 72 144 288 Usable Gates 800 1600 3200 6400 t pd ( ns) XC9500XL 5 7.5 t pd ( ns) XC9500XV 4 5 6 Registers 36 72 144 288 f SYSTEM XC9500XL XC9500XV 178 200 125 151 Packages PC44 CS48 VQ44* VQ64 TQ100 TQ144 CS144 PQ208 BG256 FG256* CS280*

XC9500 5V Family XC9536 XC9572 XC95108 XC95144 XC95216 XC95288
Macrocells 36 72 108 144 216 288 Usable Gates 800 1600 2400 3200 4800 6400 5 7.5 7.5 7.5 tPD (ns) 15 10 36 72 108 144 288 Registers 216 Max. User I/Os 34 72 108 133 192 166 Packages 44VQ 44PC 48CSP 44PC 84PC 100TQ 100PQ 84PC 100TQ 100PQ 160PQ 100TQ 100PQ 160PQ 208HQ 352BG 160PQ 208HQ 352BG

XC9500 5V Family XC9536 XC9572 XC95108 XC95144 XC95216 XC95288
Macrocells 36 72 108 144 216 288 Usable Gates 800 1600 2400 3200 4800 6400 5 7.5 7.5 7.5 10 TPD (ns) 15 36 72 108 144 216 288 Registers Max. User I/Os 34 72 108 133 166 192 Packages 44VQ 44PC 48CS 44PC 84PC 100TQ 100PQ 84PC 100TQ 100PQ 160PQ 100TQ 100PQ 160PQ 208HQ 352BG 160PQ 208HQ 352BG

XC9500XL 3.3V Family XC9536XL Macrocells Usable Gates tPD (ns)
Registers Max. User I/Os 36 72 144 800 1600 3200 5 117 Packages PC44 VQ44 CS48 VQ64 TQ100 CS144 TQ144 288 6400 6 192 PQ208 BG256 FG256 CS280 XC9572XL XC95144XL XC95288XL

XC9500XV 2.5V Family XC9536XV Macrocells Usable Gates tPD (ns)
Registers Max. User I/Os 36 72 144 800 1600 3200 5 117 Packages PC44 VQ44 CS48 TQ100 CS144 TQ144 288 6400 6 192 PQ208 FG256 CS280 XC9572XV XC95144XV XC95288XV

x XC9500/XL/XV Family Features Driving the ISP Revolution
Complete support of ISP designer’s Product Life Cycle Provides industry’s best pin-locking CPLD at lowest price Complete “state-of-the-art” software support CPLDs key part of the Xilinx “total logic solution” Benefits of ISP: No need for costly device programmers, fewer board re-spins, less scrap and re-work, reduces design and development time scales, enables field upgrades, eliminates unnecessary package handling, CPLD users are all going to ISP and Xilinx will be “driving” this ISP Revolution process with the XC9500/XL. They offer the industry’s best product life cycle support, pin-locking, architecture and software to enable this evolution to take place. No other competitor offers this complete of a solution to the CPLD market. And now, with this roadmap, CPLD users can now see the Xilinx commitment to providing the next generations of CPLD products, all which will be design to fit the users needs. x CPLD CPLD Program the whole board not each chip! 6

XC9500/XL/XV Family Features Most Complete JTAG Testability
IEEE Std boundary-scan Testability & advanced system debug/diagnosis 8 instructions supported (incl. CLAMP) Full support on all family members 1532 Industry-standard ISP interface Complete 3rd party support Benefits of JTAG: Improved testability, higher system reliability, cheaper test equipment, shorter test time, reduced spare board inventories, reduces device handling. The XC9500XL family has the most complete, industry-standard JTAG boundary-scan capabilities -- supporting an important capability for all new system designs. In addition to manufacturing test benefits, JTAG boundary-scan enhances development and debug as well, especially in complex, tightly packed systems. JTAG allows all internal nodes to be read out using only the 4 JTAG pins! The XC9500XL (along with XC9500) is the only CPLD family to support full JTAG boundary-scan in the whole CPLD family -- even lower density devices! The JTAG-based in-system programming (ISP) protocol allows compliance with emerging standards, such as the IEEE subcommittee formalizing a standard for ISP. 6

XC9500/XL/XV Family Features Innovative CSP Packaging
New 48-pin Chip Scale Package (CSP) 1/3 size VQFP-44, 82% smaller than PLCC-44 Big board space benefits New 144-pin CSP (117 user I/Os) Uses standard IR surface mounting process Supports industry’s high growth market segments Communications, Computers, Consumer Xilinx is the first PLD manufacturer to provide Chip Scale Packaging (0.8 ball spacing) to our customer base. This new packaging technology clearly meets the markets demands for providing excellent functionality in a small form factor. The CSP packages use standard surface mount attachment processes while providing the same high reliability and quality typical of the new BGA-type technology. PC44 5.6X

XC9500/XL/XV Family Features New price points open up new apps
Motherboards for PCs and servers PC peripherals and add-on cards DVD players/controller cards Graphics cards Automotive Engine control Automotive navigation systems (GPS) Consumer LAN / DSLAM Video Games/Toys These new cost points, supported by our technology and supply chain management strategies, allow users that haven’t designed with CPLDs previous now to do so. Densities, ease-of-use and now lower prices make CPLDs the logic of choice for almost every cost sensitive application.

Ease of use Improved CPLD process flow Single process (Implement Design) will pull the design through the entire fitting process Granular control still possible for power users by expanding individual processes New design creation aids New project wizard leads the user through the project creation process Add existing source / Create new source processes - assist in getting started faster Centralized process properties menu Web Update Built in utility checks for service packs and supplemental CPLD updates Downloads and installs update in single step CoolRunner XPLA3 Product Overview File Number Here

XCR3000XL Family Features Overview
High fMAX = 200MHz Fast TPD = 5nS Instant productivity software tools Best ISP/JTAG support World’s Smallest BGAs (CP56) Industry’s 1st & most efficient architecture - PLA Ultra low power operation No power/performance tradeoffs Low Power = High Reliability CPLD Designer Needs High Performance Time to Market Package offering Low power The Xilinx CoolRunner XCR3000/XL devices are fast and offer the same time to market advantages as the XC9500/XL families but at really LOW POWER! How low? For a 128 macrocell device, the standby current (no action inside the chip) is as much as 60mA for competitive CPLDs but only 22mA for CoolRunner! (That’s 3000 times less power!!) And at 50MHz, the competition can be as high as 80mA, but CoolRunner is less than 20mA! Xilinx achieves these incredibly low power numbers because CoolRunner devices are the industry’s first and most efficient architecture. THESE PARTS ARE FOR LOW POWER APPLICATIONS!

CoolRunner XPLA3 Family

XCR3000XL Family Features Low Power
Dynamic Battery Life Populated with 16 bit 20MHz 2 AA batteries Non CoolRunner devices in low power mode 20 40 60 80 100 120 140 160 180 200 Hours of operation CY37128 M4A3 M4LV 7000A 3000A ISPLSI2128VE XC95144XL XCR3128XL Competitive Device Families Longer battery life is one of the big benefits of low power devices. Using only 2 AA batteries, 16 bit counters were configured in 8 different CPLDs at 20 MHz and we waited … Even with the non CoolRunner devices in low power mode, the results are stunning! The XCR3000XL devices lasted more than 5 times longer than any other part! 3.3V CPLD Low Power Leadership! 6

XCR3000XL Family Features Extra ‘Hidden’ Benefits of Low Power
Eliminates Expensive Heat Sinks & Cooling Fans Heat Sinks: $ $ 12.00 Fans: $ 3.50 and up Decreases Power supply component size for: High Performance Small Portable Form Factors Computing Lap & Palm Enclosures Higher product density With CoolRunner’s low power, the designer can eliminate expensive heat sinks and fans, significant bill of material items. Reducing the power supply means even more savings. And the low power is often a necessity for high performance and small portable form-factor applications. Less heat means higher performance, cost savings and increased reliability. Less Heat = Higher Performance, Cost Savings & Reliability! 6

Thermal Emissions Comparison
25 30 35 40 45 50 55 60 Degrees Centigrade Ambient Xilinx XCR3256XL-7TC144 Cypress CY37256VP AC Lattice M4LV-128/64-10YC Altera EPM7256AETC144-7 Altera EPM3256ATC144-7 Lattice ispLSI2192VE-100LT128 Devices programmed with 16 bit counters with the MSB brought out to an LED and operated at 50MHz Where applicable, competitive devices were in non-turbo mode Note the MACH4 device is 128 macrocells, Lattice is 192 macrocells (largest in the family)

Thermal Characteristics
Altera 3K Test IR00004.ISI The Altera MAX3000A 256 macrocell device was powered up in low power mode and loaded with a 16 bit counter and clocked at 50MHz. A thermal imaging camera measured the Altera device (P1) to 40.23ºC, (P2) was a CoolRunner XCR3256XL 30.03ºC, the back ground temperature was 22.88ºC (P3)

Higher System Reliability
FITS Time Infant Mortality Constant Failure Wear out Temperature Activation Energy EA Aggravated by Temperature! Increased Temperature = Decreased Reliability

Lower Power = Smaller Packages
XPLA3 supports small industry standard packages New Chip Scale Packaging CS48 CP56 44 PLCC 44 VQ 17.6 mm 48 CS 56 CP 12 mm 6 mm 7 mm Low power consumption also allows for some pretty cool packaging options. Note the size difference between the standard 44 pin PLCC shown in blue and the two chip scale packages offered in the lower density CoolRunner XPLA3 CPLDs.

High Performance and Ultra Low Power
The RealDigital CPLD A New Class of CPLD with High Performance and Ultra Low Power without Compromise! CoolRunner-II is the only CPLD that combines both high speed and ultra low power operation. With the speed of the 9500XV and lower power performance than XPLA3, this new era of CPLDs will establish itself as the leading edge process technology for future CPLDs from Xilinx. A new class of CPLD from Xilinx with high performance (speed plus advanced feature set) and ultra low power without a price compromise. The best CPLD solution available.

CPLD Sense amp Designs Have Migration Limits
3.3 Volt Devices 2.5 Volt 0.18µ 0.25µ 0.35µ 0.50µ 0.60µ 1.8 Volt, 0.18µ 5.0 Volt High speed and low power barrier Sense amps don’t scale well CR-II FZP Xilinx’ patented technology enables CR-II to confidently and effectively scale the technology down past 0.25microns. Other sense amp technologies, due to the inability to scale effectively down to 0.18u and beyond, hits the proverbial “brick wall”. Because of the circuit overhead that is involved with traditional sense-amp architectures cannot scale down as fast as the logic portion of the silicon. These process technologies will have a difficult time getting to 0.18u and may not be able to scale any further. Xilinx FZP technology eliminates the overhead, therefore there is no limitations on how far we can go. Advantage Xilinx. Sense amp based CPLD technologies don’t scale effectively beyond 0.18µ

High Level Architecture
Clock and Control Signals I/O Blocks I/O Function Block 1 AIM Block n 16 40 16 FB Fast Inputs MC1 MC2 MC16 PLA Very traditional architecture incorporating PAL-like function blocks interconnected with the Advanced Interconnect Matrix (AIM). Note the boundary scan/ISP controller delivers the usual in system programming, but all density parts will program in one second or less. All charge pump circuitry is contained on board. The number of function blocks will depend on the density/size of the device. For instance the 32 macrocell CoolRunner-II will have 2 function blocks, while the 384 macrocell CPLD will have 24 function blocks.

Function Block Architecture
PLA Array 40x56 From AIM 40 56 Product Terms MC 1 MC 16 Global Clocks Global Set/Reset 16 3 To I/O Block Feedback to AIM The PLA array has 40 input signals from the AIM. The signals are then inverted in the function block in order to have true and complement values available. The PLA is 40x 56 terms wide. The product terms are not dedicated to a particular macrocell, but shared within the function block. The available 56 product terms can be used for data and control functions, including clocking, reset, set, and output enables. Each function block has 16 macrocells. All global set, reset, and clock signals are available at each macrocell. The output from the macrocell goes both directly to the I/O block as well as feedback to the AIM for use in other logic.

Logic Allocation Advantage
PAL: Requires 4 product terms! PLA: Requires only 3 product terms! B C A X Y A B C Can NOT share common logic X = A & B # C Y = A & B # !C X Y Indicates ‘unused’ junction Indicates ‘fixed’ junction Indicates ‘used’ junction Common logic may be shared in CoolRunner-II

Macrocell Architecture
FB Inputs from AIM application notes: 40 PLA Array 49 P terms Macrocell 4 Control Terms from I/O Block (Fast Input) Feedback to AIM PTA PTA CTS GSR GND PTB VCC to I/O PTC GND S D/T Q Here is the basic building block. All macrocells are the same with the exception that buried macrocells do not go to an I/O. Note the PLA structure (upper left) delivering up to 56 p-terms to a given site. The muxes are programmed to select as needed by the design software. The flop can be configured with D,T or latch capability. Clock polarity can be selected per macrocell. Clocks can be attached directly, or locally doubled. More on this later. FIF Latch DualEDGE GCK0 PTC CE GCK1 CK CTC GCK2 R PTC PTA CTR GSR GND

I/O Block Characteristics
VREF for Local Bank HSTL & SSTL VCCIO VREF to AIM I/O Pin 128 macrocell and larger devices Input Hysteresis to Macrocell (Fast Input) 3.3V - 1.5V Input Weak Pullup/Bus Hold Slewrate VCCIO from Macrocell I/O Pin The I/O block is responsible for multiplexing between the output buffer and data entering the CPLD via the pin. The I/O block can be configured as an input, output, or both. The output enable mux is software selectable with the OE option including: enabled, disabled, product term B, control term, open drain, CGND, or one of 4 global OE signals. The input structure in CoolRunner-II allows several options to the designer. The input can be configured to have hysteresis, if selected, for noisy or slow edge rate signals. Each pin can be individually configured to have hysteresis or not. This improves noise margin at very low logic signal levels and improves the ability to make clocks with minimal external circuitry (maybe on the clocks). Or the I/O block can read an SSTL or HSTL input signal. The SSTL and HSTL standard is available on the 128 macrocell and larger densities. For the required VREF in SSTL and HSTL standards, a additional pin must be dedicated to providing the reference voltage. A pin when dedicated to this function drive the VREF bus throughout the entire I/O bank. A VREF pin must be specified of each I/O bank. The inputs can come in and directly attach to the D input of the flip flop to act as a fast input register or feed into the AIM array. The I/Os are configured to range across multiple 3.3V to 1.5V I/O standards. Enabled Control Term PTB 4 / GTS[0:3] CGND Open Drain Disabled

Input hysteresis control
I/O Flexibility XC2C32 XC2C64 XC2C128 XC2C256 XC2C384 XC2C512 I/O Banks 1 2 4 LVTTL33, LVCMOS 18, 25, 33 & 15*I/O SSTL3-1(3.3v), SSTL2-1 (2.5v), HSTL1 (1.5v) Input hysteresis control Slew rate control CoolCLOCK DataGATE Clock doubler Clock divider Bus hold output Hot pluggable  This is the planned BladeRunner line-up. 32 to 512 macrocells with up to 3.5ns tPD performance. Also note the wide choice of features like input hysteresis, bus hold, slew rate control and clocking features. With this feature set, there should be little reason not to use CR-II CPLD solutions. Please note that 1.5v I/Os are not LVCMOS compatible. Note: 1.5v inputs need hysteresis

RealDigital Design Advantage
Turbo vs Non Turbo Larger R = slower response & less power RealDigital: CMOS Everywhere - Zero Static Power C B A D Vcc A B C Sense amplifier 0.25mA each - Standby Higher ICC at Fmax Traditional CPLDs - bipolar sense amp product terms Always consumes power Even at standby Performance is traded for power consumption as devices get larger CoolRunner-II RealDigital design uses 100% CMOS for product terms Virtually no standby current Combines high performance & ultra low power No power limits on device size

Note: 128 MC device estimate
Reducing Power Icc = C x V x f To reduce power: Lower capacitance Lower voltage Lower frequency 0.18 m lowers capacitance Low 1.8V How can we reduce the frequency? Traditional Sense Amp Designs Frequency 1.8 Volt (est) 2.5 Volt 3.3 Volt ~ 200MHz ~ 200mA Note: 128 MC device estimate ~ 100mA Icc Standard CMOS ICC equation. Note the curve on the bottom shows this behavior, but it fails to tell you how to get to zero. To take a CMOS product to zero, you basically have to stop the inputs from switching. This isn’t easy! By transitioning CoolRunner-II to 0.18 micron process, capacitance is lowered as well as operating voltage. Vcc can be 1.8V. So how else does CoolRunner-II lower power. 1) by implementing the CoolRunner patented chain of gates structure known as FZP. 2) by allowing customers to lower frequency (using clock divider and CoolCLOCK) One feature that is really important: Note how sense amp CPLDs increase in quiescent current when the voltage drops. So even if you are decreasing voltage, the power does not decrease in a linear fashion. CoolRunner devices provide an additional power savings in that the current consumption also decreases. Only the Fast Zero Power technology allows this!

Low Power CPLDs And our parts still run on GRAPEFRUIT!
CoolRunner XPLA3 Low power 3.3V core with 5V tolerance CoolRunner II Ultra Low Power Lowest Cost Feature Rich 1.8V core with 1.5v to 3.3V compatibility And our parts still run on GRAPEFRUIT!

Beware! Not all ‘Low Power’ Logic is Created Equal!
Some logic devices have ‘power down’ modes Complicates timing models (non-deterministic) Power down modes slow timing (TPD / Fmax) when used Some logic devices ‘shut down’ when not active Latency periods apply for wakeup (typ. 50ns) No power savings when operating Choose Logic to simplify design process No speed / power tradeoffs Simple timing models

500mV Input Hysteresis Supports simple oscillation schemes
Ideal for slow edge rate, noisy signals Analog comparators & sensors Hall effect switches IR inputs R/C oscillators Eliminate external Schmitt trigger buffers Reduces power consumption with slow signals V CoolRunner-II _ In + CoolRunner-II

Solving Signal Integrity Challenges
Noisy, slow analog signals Hall Sensor R/C Oscillator XTAL input RFI, EMI effects Input hysteresis If your board design contains slow or noise susceptible signaling, there is finally a cure without adding additional components to your PCB. With input hysteresis, signal integrity challenges are held at bay by squaring up those slow switching signal nightmares. Not only can you directly interface Hall Sensors and slow ramping RC Oscillator signals to our CPLDs but it will save you power. Thanks to input hysteresis, these slow transitioning analog signals will spend less time in the transition zone (or high current draw zone) and be switched high or low to resemble a real digital signal. Don’t forget input hysteresis helps in 2 ways: 1. Improve signal integrity 2. Allow the use of a oscillator and RC network to form a inexpensive clock signal With input hysteresis Analog signals function as digital inputs Saves power by non-linear operation Added noise immunity

DualEDGE: Performance Enhancing
In all CoolRunner-II devices Edge detect doubles clock up to 500MHz Selectable on a per macrocell basis Ideal for Double Data Rate (DDR) memory devices Doubler With the emergence of Double Data Rate (DDR) memory devices, the CoolRunner-II clock doubler delivers a efficient method to gluelessly interface to memory devices. With speeds surpassing 400MHz, high speed interfaces problems are a thing of the past. Remember, this clock performance beats any CPLD competition and offers it at lower power. NOTE: CoolRunner-II clock doubler operates as a pulse detector and does not have a 50/50 duty cycle.

Clock Divider: Power Efficient
128, 256, 384 & 512 macrocell 2,4,6,8,10,12,14 or 16 digital clock divide Reduce external oscillators 50% duty cycle Reduces cross talk CoolRunner-II offers the most sophisticated CPLD clock resources. With a clock divider circuit, you can select 1 of 9 different clock frequency (including the original frequency with the clock doubler) divisions of the incoming clock signal. Since this generates another clock signal, it saves logic and simplifies board design. One other benefit is reduced chance for RFI problems by eliminating cross talk between clock signals. System Clock Sync Reset Div_clock Phase bit = 0 Div_clock Phase bit = 1 Divide by 4

CoolCLOCK Further power reduction plus performance
Combination of clock divider & DualEDGE (clock doubler) Divide incoming clock by two (lowing total power), then double at macrocell for high speed requirements CPLD Global Macrocell Divider Input Divide by 2 Doubler CoolCLOCK is a idea to reduce power consumption via the clocking features in CR-II. As seen from the figure, a divide by 2 is selected to reduce power consumption in the device while the clock doubler is employed at the output macrocell to maintain original performance goals. This is in addition to the already low power operation achieved with FZP. Original frequency Output

DataGATE control signal
Another low power enhancement Control DataGATE signal externally or internally User programmable on/off switch for specific inputs Only enable inputs when necessary Great for power reduction on wide logic interfaces Latch data when valid, reduces unnecessary signal toggling DataGATE Diagram DataGATE is a new, low power idea fostered by trying to only use I/O signals when necessary. In a normal designs, address and data busses are connected to multiple devices. Only at certain points in time do these devices care about what the bus contains. With DataGATE, the excess bus toggles are eliminated and thus power is reduced in the CPLD. DataGATE is a control signal in the CoolRunner-II CPLD that can be enabled or disabled on a per macrocell basis. This gives the designer the flexibility to use or not use DataGATE. In critical low power application, DataGATE can significantly lower power consumption (theoretical possibilities are 90%!!). The more DataGATE signals, the lower the power consumption. DataGATE control signal Gated internal signal Input pin

The Best Design Security
Easy To Use New Capabilities 1532 in system programming JTAG boundary scan Fast Programming times Multiple levels of security Affect different mechanisms Interconnects are buried Multiple security signals Scattered and layered Xilinx WebPACK™or Foundation ISE Software

RealDigital CPLD Advantage
CoolRunner-II, the RealDigital CPLD provides the customer with a total solution that includes leadership in design technology, system features and software. It provides a 1.8 volt all digital core with a 0.18 micron scalable process, up to 303 MHz performance and typical power consumption at 20mA standby. CoolRunner-II also includes a host of system features that interface to the “real” analog world and easy to use single solution software.

Chip Scale Packaging Leadership
17.6 mm 44 PLCC 12 mm 44 VQFP 8 mm 17.6 mm 132 CP 12 mm 56 CP 8 mm Supports high-growth market segments: Communications, Computers, Consumer, especially wireless 6 mm 6 mm Xilinx has lead the industry again with the introduction of the small, space-efficient Chip Scale Package. The CSP solutions are available on all CR-II family members. Remember that these smaller package are ideal for portable equipment but come with a cost adder Uses standard IR techniques for mounting to PC board

Lower Power = Smaller Packages
56-Ball 0.5mm CSP Provides 44 I/O’s 0.5mm pitch 36 mm2 footprint Ideal for handheld & portable applications PDAs Portable PCs Cellular Phones Telecom & Networking Equipment Network Appliances

Best Package Offering for High Volume Applications
CP56 (6 x 6mm) Smallest form factor chip scale packages Optimized packaging Smallest size chip scale Highest performance BGA Highest I/O count Small size Lowest cost flat pack CP132 (8 x 8mm) VQ44 (10 x 10mm) VQ100 (14 x 14mm) FT256 (17 x 17mm) PC44 (16.5 x 16.5mm) Small form factor, highest performance, BGA packages CoolRunner-II offers a variety of package solutions. From 6mx6mm chip scale 56 ball package to 23mmx23mm chip scale 324 ball packages. TQ144 (20 x 20mm) FG324 (23 x 23mm) PQ208 (28 x 28mm) Package widths drawn to scale.

CoolRunner-II Family Overview

PDA: CoolRunner Reference Design Example
Battery Flash SRAM Compact Flash Battery SMBus IrDA LED LED Microprocessor P Docking Cradle UART Docking Cradle LCD LCD SPI DragonBall or StrongArm, today’s PDAs have a lot in common. All need memory and EPROM for the basic PIM. Also, there is an interactive LCD interface and more are adding in external busing to permit add-on goodies- like cameras, GPS units, telephones, b interfaces and so-forth. CoolRunner-II handles them all. Keypad Touch Screen Indicates a CoolCORE

Exploiting Our Technology Lead
0.35 0.25 0.18 0.13 0.09 0.07 CPLDs Feature Size (micron) Clipper Xilinx is the technology leader in FPGAs design and is aggressively applying that leadership to its CPLD development FPGAs Schooner

XCR3000XL & XC2C Low Power Features Open Up New Applications
Telecom “Neighborhood” Multiplexors Bay Stations Routers Multiplexors PBXs WLAN Central office switches Speech recognition systems PC Peripheral PCMCIA cards Portable computer displays White board scanners Memory cards High Performance Workstations and servers Video graphics cards Storage Systems Portable / Consumer PDAs Cell phones MP3 players Laptops Docking stations Battery powered scanners PDA add-on modules Digital cameras Portable dictation systems Gas meters Handheld meters Smart Card Readers Payphones Medical Portable syringe pump Home monitoring system Blood analyzer The incredibly low power of the CoolRunner families opens up new applications not previous possible with other devices. These include the obvious portable consumer products like PDAs and handheld meters. But there are also medical, telecom, PC peripheral and high performance applications just perfect for a CoolRunner device!

One Ultimate CPLD Solution for All Designs
High Performance 3.0ns TPD, FMAX 385Mhz Improved features Low Cost 0.18µ = small die size Lowest cost packaging Lowest Power 9.9mW 16µA typical stand-by High performance and ultra low power without a price premium now provide designers a single product that is ideal for a wide spectrum of applications, meeting the demand for high performance, cost competitiveness and is the perfect fit in ultra low power applications. CoolRunner-II meets the demands for performance in markets like telecomm and datacomm, while being cost competitive enough for the consumer market and provides the ultra low power consumption required for the battery powered portable market. Even though not all of these applications require low power many of the designers for high performance applications have a system power budget. The CoolRunner-II ultra low power capability helps them meet their power budgets. Storage Systems, Routers Set-Top Box, Cell phone Handheld, Portable Equipment

IQ CPLDs for Industrial and Automotive Applications

Introducing IQTM Products
Why IQ? New range of devices with an extended Industrial Temperature option Consists of CPLD and FPGA families already available in I Grade - and the addition of selected devices with an extended temperature ‘Q’ grade option IQ - it’s the intelligent choice for Automotive designers!! For FPGAs Q grade means: -40°C to +125°C Junction Temperature For CPLDs Q Grade means: -40°C to +125°C Ambient Temperature Ambient = the temperature of the air surrounding the device Junction = is the temperature of the die in the package

Industrial and Automotive CPLDs
Density 512mc Low power 5V tolerant Small packaging 2.5V Lowest power Highest speed Advanced features Additional security Smallest packages Lowest cost 3.3V tolerant 1.5V compatible Up to 4 I/O banks 288mc Lowest cost 3.3V 5V tolerant Small packaging 3.3V tolerant Small packaging Up to 4 I/O banks 3.3V 2.5V 1.8V Core Voltage

Ease of use Improved CPLD process flow Single process (Implement Design) will pull the design through the entire fitting process Granular control still possible for power users by expanding individual processes New design creation aids New project wizard leads the user through the project creation process Add existing source / Create new source processes - assist in getting started faster Centralized process properties menu Web Update Built in utility checks for service packs and supplemental CPLD updates Downloads and installs update in single step CPLD Software Update and Online Support File Number Here

Xilinx Online Software Solutions
Web-deliverable desktop and online design solutions for new, high volume markets Industry’s broadest PLD product offering in a single downloadable solution Enables fastest time-to-market Easy to use design tools Easy to obtain via the web No license required Software upgrades available for online purchase Xilinx online products offer designers a zero cost of entry into programmable logic. Of the free PLD software on the market, the Xilinx online software supports the highest density of devices . Unlike it’s competition, the online software requires no license, enabling designers to immediately start programming.

ISE 6.1i Software Improvements Ease of Use
Improved CPLD process flow Single process (Implement Design) will pull the design through the entire fitting process Detailed control still possible for power users by expanding individual processes New design creation aids New project wizard leads the user through the project creation process Add existing source / create new source processes - assist in getting started faster Centralized process properties menu

ISE 6.1i Software Improvements
Web updates Built in utility checks for service packs and supplemental CPLD updates Downloads and installs update in single step

ISE 6.1i Software Improvements
HTML report improvements Integrated browser in the project navigator environment Addition of the timing report to HTML format Improved graphical presentation and equation representation CPLD support in PACE Pin Assignment and Constraint Editor

What’s New in ISE 6.1i CoolRunner-II Saturn support
Supported in XPower Saturn support All devices in all ISE configurations ISE WebPACK availability Web release on Sept 22 Free CDs available from the Xilinx Online Store Shipping charges apply 3,400 downloads per month and growing! The ISE 6.1i release will offer support for the upcoming CoolRunner-IIs family of CPLDs. This continues the Xilinx tradition of “software before silicon”. Xpower will be improved to include both CoolRunner-II and CoolRunner-IIs. This further strengthens the collection of Xilinx Power Tools which also includes Spreadsheet Power Tools and Web Power Tools. Customers can learn more about these exclusive power management tools at ISE WebPACK continues to be the leader in free, downloadable CPLD tools. Download statistics continue to increase. Registrations continue to grow with the inclusion of ISE WebPACK in sales campaigns such as the CoolRunner-II design kits. In addition, customers can request a free ISE WebPACK CD when download is a problem. These requests are fulfilled from the Xilinx Online Store. The CD is free but shipping charges apply (NA-$5.85 / Japan-$19.99). These requests are fulfilled with an ISE Evaluation Kit. Instructions are included describing the process for installing either ISE WebPACK or the full ISE Evaluation. Kit includes ISE installation CDs, MXE-II, and HDL Designers Guide tutorial.

Buy Products Online Links to the Xilinx eCommerce page From WebFITTER
From WebPACK

Additional Web Based Information
For additional CoolRunner-II product information For other Xilinx CPLD related product information For CoolRunner-II resource CD After this brief introduction to the new CoolRunner-II product family, these web locations can help answer many additional product or application related questions. All information on xilinx.com will be live on January 14, 2002.

Ease of use Improved CPLD process flow Single process (Implement Design) will pull the design through the entire fitting process Granular control still possible for power users by expanding individual processes New design creation aids New project wizard leads the user through the project creation process Add existing source / Create new source processes - assist in getting started faster Centralized process properties menu Web Update Built in utility checks for service packs and supplemental CPLD updates Downloads and installs update in single step Customer Success Stories File Number Here

CPLD Success Stories Customer 1
Design Win Factors Market: Automotive Application: Digital Audio Broadcast Car Radio Device: XC9572XL-10TQ100I Competition: Lattice Reasons: Pin Locking Pricing Easy to use software High Performance Time to Market Fit in Existing Flow Package offering 5v & 3.3v Low cost Low power

Design Win Factors High Performance Time to Market Fit in Existing Flow Package offering 5v & 3.3v Low cost Low power Market: Datacom Application: Switching Host Board Processor Devices: XC95144XL-10TQ100C Competition: ASIC Reasons: High performance Pin-locking Flexible interface I/Os

Design Win Factors High Performance Time to Market Fit in Existing Flow Package offering 5v & 3.3v Low cost Low power Market: Consumer Application: MP3 Player Device: XCR3032A-VQ44C Competition: None, no one could meet low power Reasons: Low power Low Cost, small package Web-based software

Design Win Factors Market: Consumer Application: Fingerprint Point-of-Sale Terminal Device: XC95216 Competition: None Reasons: On-the-fly changes 133 MHz performance Pin-locking Superior technical support High Performance Time to Market Fit in Existing Flow Package offering 5v & 3.3v Low cost Low power

Design Win Factors High Performance Time to Market Fit in Existing Flow Package offering 5v & 3.3v Low cost Low power Market: Commercial Application: Hand-held Cable TV Tester Device: XC95288XL Competition: Quicklogic Reasons: Design Flexibility Price Performance

Design Win Factors High Performance Time to Market Fit in Existing Flow Package offering 5v & 3.3v Low cost Low power Market: Telecom Application: Voice Synthesis Server Module Device: XCR3128 Competition: Lattice Reasons: Power!

Design Win Factors Market: Instrumentation Application: Microcontroller Emulator Device: XCR3128VQ100C Competition: Altera Reasons: Power Performance ISP Capabilities High Performance Time to Market Fit in Existing Flow Package offering 5v & 3.3v Low cost Low power

5V 3.3V 2.5V LOW LOW POWER POWER 3.3V 1.8V XC9500 Portable Consumer
Remote Controls Digital Cameras PDAs Smart Phones Test Equipment Web Pads Medical Equipment Label Printers Mobile phone add-ons MP3 Players Web pads Payphones Smart Card Readers Hand Held Games USB Applications Utility Meters Data Logger Portable PDAs Remote Controls Test Equipment Medical Consumer Cell Phones MP3 Players Set Top Box Hand Held Games High Speed Telecom Switches Routers Motor Control Test Equipment Security Systems Cable Modems Car Nav. Systems Cash Registers Surveillance cameras Set Top Boxes Access Controls Fax Machines Gaming Machines Industrial Control Tape Drives Power Supplies Modems Access Controls Fax Machines Gaming Machines Industrial Control DAB Car Radios TFT LCD Interface Radio Comms Train Controller Slot Machine Digital Printer Telecomm Base Stations Encoders Decoders DECT Phones Line Cards Industrial Control XC9500 5v, macrocells Low Cost 5ns / 200MHz Best Pin Locking JTAG High Endurance (10,000 program cycles) 2.5v, macrocells Low Cost Best Pin Locking JTAG High Performance High Endurance 20 year data retention 4ns / 250 MHz 3.3v, macrocells Low Power JTAG Logic Flexibility 5ns / 200MHz Static power <100uA 20 year data retention 5V tolerant I/Os 1.8v, macrocells Ultra Low Power Schmitt Trigger Inputs CoolCLOCK, DataGate 3.5ns / 303MHz Static power <100uA I/Os - LVTTL, LVCMOS SSTL & HSTL 3.3v, macrocells Low Cost Best Pin Locking JTAG High Performance High Endurance 5ns / 200MHz

Xilinx CPLD Summary XC9500/XL/XV fast, higher voltage, low-cost
For mainstream 5v, 3.3v & 2.5v designs Great architectural features (ISP, JTAG, pin-locking) Coolrunner XPLA3 low power Pioneering low power 3.3v product with 5v tolerant I/O Lowest power 3.3v CPLD - 3x better than nearest 3.3v competitor CoolRunner-II High Performance and Low Power Higher Performance & High Speed (385MHz) at 1.8V Enhanced clocking & I/O feature set Lowest power consumption DataGATE for even lower power operation Higher system reliability & system security

Introduction to Xilinx CPLDs

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