1. CoolRunner™ CPLD Overview
Steve Prokosch

2. The CoolRunner Advantage
Industry’s lowest power CPLDs
Fast Zero PowerTM means best performance and power
High speed Tpd 6 ns
Standby current < 0.1 mA
Improved system reliability
Revolutionary XPLA architecture
Exceptional routability & pin-locking
Fast deterministic timing
3.3 and 5.0 volt devices available
Small form factor packaging
Full software support
Fast Zero Power means that no part in the CoolRunner CPLD family draws more than 100 uA of power during quiescent operation. No 'power down' tricks are used to achieve this result; the low power consumption (true CMOS operation) is achieved through the innovative application of a technology which will be described later in this presentation. CoolRunner devices have the distinct advantage of being able to use small form factor packages to provide designers with the highest density CPLD solutions.
The XPLA Architecture affords a programmable logic designer capabilities never before realized in a CPLD. Early pin locking, late design changes, the widest product term logic available, and simple timing coupled with an ISP friendly architecture make the CoolRunner a powerful choice for any programmable logic design. 2

3. CoolRunner Families
Advanced
Feature!
Coming
Soon
XPLATM
XPLAEnhanced
XPLA2
XPLA3
3.3 Volt Zero Power
0.35u EECMOS
Up to MCs
3.3 Volt Zero Power
0.35 um SRAM
MCs
3.3 Volt Zero Power
0.35um EECMOS
32, 64, 128 MCs
3.3 V
0.5um EECMOS
32, 64, 128 MCs
22V10
This slide is an overview of the FZP current and anticipated logic offerings. The first FZP family, the Standard XPLA1 CPLD is based on 0.5u CMOS and has 5V and 3V members from 32 to 128 macrocells in a variety of package offerings, across both commercial and industrial temperature ranges.
XPLA Enhanced takes the existing XPLA1 components, and adds additional clock resources and ISP. This family is further expanded by porting the components onto a 0.35u process, which lowers cost and increases speed. This new design also provides for the capability of 5 Volt tolerance for these 3 Volt parts. For low voltage aficionados, the AS family (0.35 u parts) will include an industrial component characterized and tested at 2.7 Volts.
The XPLA2 family is a SRAM based technology comprised of two family members, the 320 macrocell and the 960 macrocell parts.
XPLA3 is the latest addition to the FZP CPLD family, and will offer a wide range of component densities, ISP, EE CMOS, high speed, and a high density/low cost solution for programmable logic designers.
5.0 Volt Zero Power
0.5um EECMOS
32, 64, 128 MCs
5.0 V
0.5um EECMOS
32, 64, 128 MCs
22V10

4. XPLATM Architecture Central ZIA is Virtual Crosspoint Switch
Logic Block
MC15
MC0
MC1
I/O 36 16
Logic Block
MC15
MC0
MC2
I/O 36 16
36 ZIA Inputs
Control 6
ZIA To 16
Macrocells
Logic Block
MC15
MC0
MC1
I/O 36 16
Logic Block
MC15
MC0
MC2
I/O 36 16 5
PAL
Array
64 macrocell block diagram
Central ZIA is Virtual Crosspoint Switch
Patented combination of PAL and PLA structures
Flexible routing
Deterministic timing
Here is an elevated overview of the basic architecture. It looks very similar to competing architectures, in that there are several logic blocks arranged around a virtual crosspoint switch (the ZIA for Zero power Interconnect Array). When you push down into the logic block however, the unique features of the XPLA architecture become apparent.
The XPLA Architecture is based upon the union of a PAL structure and a PLA structure, which provides a tremendous flexibility for logic designers.
In the XPLA Architecture, each of the 16 macrocells in a logic block have fully symmetrical logic resources, tremendous product term width (up to 37 wide in a single pass), and a flexibility that can only be provided by a PLA.
An additional benefit of the XPLA architecture is the ability to share product terms across multiple outputs.
PLA
Array
( 32 ) 4

5. The XPLATM Difference A Better Architecture
CoolRunner CPLDs combine PAL and PLA arrays allowing product terms to be shared 5
PAL
Array
Easy design changes
Pin-outs maintained
Deterministic timing
Great ISP
Logic resources allocated with efficiency
Complex logic in the PLA
Up to 37 wide p-terms in 1 macrocell
Common feedback terms shared
...
Notice how PLA logic can also be 'shared' across multiple macrocells, allowing for additional 'virtual density' to be realized in the instances where common logic occurs, such as in state machines and decoders. This logic can be built up one time and placed where it is needed, as it needed with no duplicated logic or granularity related losses.
The PLA logic can be thought of as a 'pool' of logic resources; these resources can be used at any time and placed on any output. This allows for tremendous design flexibility and facilitates both early pin locking and late design changes.
This flexibility in logic allocation is the reason that CoolRunner CPLD's are the leader in ease of use and ISP 'friendliness'.
PLA
Array
( 32 )

6. XPLATM CPLD Macrocell
Original XPLA Macrocell
XPLA Enhanced Macrocell
To ZIA
D / T Q
INIT
(P or R)
To ZIA
GND
GTS
CT3
CT2
CT4
CT5
Vcc
CT0
CT1
CLK0
CLK1
CLK2
CLK3
D / T Q
INIT
(P or R)
GTS
CLK0
CLK1
CT2
GND
CT0
CT1
GND
CT3
CT4
CT5
CLK2
CLK3
Vcc
GND
An examination of the CoolRunner macrocell illustrates a union of flexibility and concise, simple design. Each register can be configured as a 'D' or 'T' type register, capable of being clocked either by the rising or falling edge of a clock (programmable at each macrocell). Either a combinatorial or registered output may be chosen as an output, with a feedback path before and after a tri-stateable output buffer (which enables the implementation of bi-directional pins). Abundant output enables exist for bus interfacing, and a Global Tri State (GTS) feature exists for test or special design use.
In the XPLA1 Enhanced components, additional clock resources are implemented for instances where asynchronous clocking is required. These enhanced clock features are asynchronous product or sum terms that may be used either as additional clocks or as output enables.
Enhanced devices have extra product term clock resources
32 macrocell devices have two global clocks
Programmable clock polarity at every macrocell
D/T configurable flip-flops
Asynchronous preset, reset, and output enable controls 6

7. XPLA Enhanced Architecture
Enhanced Clocking
Adds 2 p-term clocks per logic block
Up to 6, 12 & 20 clocks on 32, 64 & 128 macrocell devices
In System Programmability in all devices
JTAG port for programming
Supports BYPASS and IDCODE commands
3 volt devices on 0.35u process
Fast as 5 volt parts
5 volt tolerant I/Os
Introducing microBGAs
64 macrocell Enhanced architecture
44 I/O in 56 LFBGA package
In addition to Enhanced Clocking capabilities, designers have been provided with ISP in lower density devices (now including 32 and 64 macrocell parts) and a JTAG port for device insertion into any JTAG chain.
The new 'AS' parts (available in 32,64 and 128 macrocells) are also Enhanced Architecture devices, and are fabricated on the 0.35 micron technology. This provides faster speed (achieving speed parity with the current 5 Volt parts) and a reduced cost for users.
Additionally, the 64 macrocell device will also be available in the 56 LFBGA package, providing 44 I/O's in a surface area of approximately square inches!

8. XPLA2 Overview Fast Module 320 macrocell CPLD!
Logic Block
MC19
MC0
MC2
I/O 36 16
MC1 64
Global ZIA
Fast Module
Local ZIA 2
Global ZIA
Local
ZIA
320 macrocell CPLD!
80 macrocell Fast Modules
ZIA’s are Virtual Crosspoint Switches
Deterministic Timing Delays
2.0ns GZIA delay
The XPLA2 family takes the same architectural features and benefits and expands the device density to 320 and 960 macrocells. This family uses ‘Fast Modules’ (FM) as modular building blocks; a Fast Module is a hierarchical entity with four logic blocks comprised of 20 macrocells each. Each Fast Module has 80 macrocells, and all FM’s are interconnected using the Global Zero power Interconnect Array.
Logic propagates through a FM (pin to pin) at a worst case timing of 7.5 ns, and use of the Global ZIA burdens the timing by a maximum of 2.0 ns (4.0 ns for the 960 macrocell device) regardless of the route through the device.
For this reason, the XPLA2 family maintains deterministic timing, and like all other CoolRunner CPLD’s, the timing of any signal path can be determined before fitting even occurs. 29

9. XPLA2 Fast Module
80 macrocells per module
20 mcs per logic block
4 logic blocks per module
LZIA/GZIA are virtual crosspoints
128 connections (64 in / 64 out) between GZIA and LZIA
36 signal fan-in per logic block
2 Global clocks per module
8 async clocks per module (2 control term clocks per logic block)
7.5 ns Tpd in module
4.0 ns fixed delay through GZIA 36 36
Local
ZIA 36 36
The XPLA2 Fast Module uses a local zero power interconnect array to locally route signals; each logic block has a fan in of 36 signals from the local ZIA.
There are 64 inputs and 64 outputs between the local ZIA and the Global ZIA, comprising a total of 128 internal connections for I/O.
Clocking resources allows for the choice of any two of the eight global clocks, and the Fast Module also has the capability of generating and using 8 asynchronous clocks. 64 64
Global ZIA

10. XPLA2 Logic Block
36 LZIA
Inputs I
Control 4 8
MC0
MC1
MC2
MC19
20 mcs per logic block
4 dedicated PAL p- terms per macrocell
32 PLA p-terms per logic block
Fast Tpds
7.5 ns Tpd through PALs
1.5 ns delay adder for PLA
8 control terms / logic block
Hardwired XOR option / each macrocell
XOR between PAL and PLA sum of product terms
PAL
Array
The logic block of the XPLA2 family is very similar to the XPLA1 devices, with a few subtle differences. There are 20 macrocells per logic block, and the number of dedicated PAL terms available to each macrocell is decreased from 5 to 4. Note that there is a hardwired exclusive OR gate preceding each macrocell and that the true or complement of the logic may be chosen by the mux.
The PLA array provides the same flexible logic resource as the PLA pool in XPLA1 parts; the XPLA2 logic allocation capability allows for product term expressions as wide as 36 to be generated with only a single level of logic.
PLA
Array
( 32 )

11. XPLA2 CPLD Macrocell
D / T Q
INIT
(P or R)
To ZIA
CT3
GND
GTS
CT2
CT4
CT5
Vcc
CT0
CT1
Clk0
Clk1
CT6
CT7
The XPLA2 macrocell functions as a conduit for combinatorial logic, or may be configured as a 'D' or 'T' type register. This register has an asynchronous Reset or Preset (but not both concurrently), and clock options that provide for programmable clock polarity at each macrocell. There are four asynchronous output enable signals, and one global tri state control for the output buffer. 6

12. The XPLA? Difference - A Better Architecture
Product Term Steering/Stealing
Product Term Sharing
36 ZIA Inputs
Control 6
Macrocell To 16
Macrocells 5
Macrocell
PAL
Array
Macrocell
Most CPLD logic allocation methods are based on some sort of a product term steering mechanism. This method has some encumbering issues;in this architecture, pin locking is jeopardized, macrocells are wasted when complex (wide) product term equations are required, and logic can not be shared across multiple macrocells without complicating the timing model.
The XPLA architecture, being comprised of both a PAL array and a PLA array, affords designers with a flexible yet straightforward allocation method. Pin lock is protected by the PLA array; any logic available in the PLA array can be presented to the input of any of the macrocells in the logic block. This structure allows for product term expressions of up to 37 wide in a single pass, reducing the necessity of internal nodes when complex expressions are required. Use of the PLA product terms results in a one time speed penalty; a two nanosecond delay (5V devices) is encountered when a single Product Term is drawn from the pool. Use of additional PT's from the PLA in the same output expression do not add any additional delays.
Macrocell
PLA
Array
( 32 )
Reduced routability - no pin locking
Complex logic burns macrocells
Indeterminate timing
Reduced logic density
Flexible routing allows 100% pin locking
No macrocells sacrificed for complex logic
Deterministic timing model
Efficient architecture increases density

13. XPLA Architecture: Superior for Complex Logic
As a comparison, if a 37 wide product term expression were required, this chart indicates the amount of macrocells that would be required internally (nodes) to create this expression, and also the time delay (tpd) which would be associated with using these architectures to build up that expression.

14. CoolRunner Timing Model
XPLA Devices and XPLA2 within a Fast Module:
Tpd_pal = Combinatorial PAL
Tpd_pla = Combinatorial PAL + PLA
Input Pin
Output Pin
Registered
Tsu_pal = PAL only
Tsu_pla = PAL + PLA
Tco D Q
clock
XPLA2 using the Global ZIA:
clock
Tpd_pal = Combinatorial PAL+ GZD
Tpd_pla = Combinatorial PAL + PLA + GZD
Input Pin
Output Pin
Registered
Tsu_pal = PAL + GZD
Tsu_pla = PAL + PLA + GZD
Tco D Q
Ease of timing calculation is a particular strength of CoolRunner devices. FZP CPLD’s do not suffer from timing cumbersome ‘features’, such as input or output routing pools, product term bypass modes, power down latency issues, or other route dependent timing complications.
There are two factors to a combinatorial timing equation: Tpd PAL, and Tpd PLA. If a logic expression is fulfilled using five product terms or less, then the timing is set purely by the PAL Tpd. If more than 5 product terms are required, logic from the PLA is used, and this will cause the propagation delay to be slowed by 2 ns (or 2.5 ns for the 3V devices). This PLA timing component is only applied once for any particular expression; a PLA increase in Tpd is applied one time, with no increased penalties for using additional PLA product terms thereafter. A product term expression with 37 product terms can have the same Tpd as an expression with only 6 PT’s.
For a registered output, the setup time is affected only by use of the PLA (if required) in the fashion detailed above and the additional Tco timing element is added to complete a registered path calculation.
The XPLA2 timing model is similar in its ease of use; the only difference is the delay added to the expression timing because of use of the Global ZIA. 16

15. The FZP Difference
Sense Amplifier
.25mA each - Standby
Higher ICC at Fmax
All other CPLD’s use CMOS sense amplifiers for p-terms
Always consumes power--even in standby
Designers must choose between high speed and low power
Limits maximum device size due to power consumption
The migration from BiCMOS to CMOS provided device designers with a technology that facilitated very dense silicon design. The CMOS technology also provided an easier platform to design upon, and had the additional benefit of low power operation. In migrating to CMOS however, designers took their BiCMOS techniques with them, and implemented product term word lines in the same fashion that they had become accustomed to.
This technique involves building up a word line using 'wired nor' inputs to a node. As more of these inputs are attached to the node, the capacitance increases, and so does the time constant. In order to speed up the propagation, this node is followed by a sense amplifier, which examines the node for approximately a 100mV change to indicate a logic level transition. This sense amplifier is effectively a linear element, so it is drawing a substantial amount of current even when not transitioning. Typical sense amplifier current consumption is on the order of 250 uA per sense amplifier. This consumption increases with increased frequency of transition also.
CoolRunner designers realized that there was a better way to implement a product term word line, and designed out the sense amplifiers. The Fast Zero Power technology is based upon a CMOS chain of gates as the base building block for CPLD logic. The primary benefit of this technique is that sense amplifiers are not used, resulting in a much lower power consumption.
High speed and low power are achieved simultaneously without tradeoff for the first time in CPLD history. This technology also allows for tremendous amounts of logic resources to be placed in very small packages. Examples of this includes a full bandwidth 22v10 in a TSSOP package, and a 64 macrocell CPLD in a 56 LFBGA offering.
FZPTM: CMOS Everywhere - Zero Static Power
CoolRunner FZPTM p- term implementation chains CMOS gates
NO standby current consumption - Fempto Amps leakage
High speed and low power together
No power limits on device size

16. The FZP Power Advantage
32 Macrocell Power Comparison PZ5032 vs Vendor A
180
160
140
Vendor A
(Turbo)
Lower power in fast
applications
120
100
Required Current (mA)
Faster in low power
applications 80
73.5 MHz.
Vendor A
(Non-Turbo) 60
Here is an example of the magnitude of power savings a user can expect to experience with CoolRunner devices. This is actual laboratory data of two 32 macrocell parts with a design consisting of two 16 bit synchronous counters. The two devices were clocked at various frequencies, and the Idd current measured and recorded.
The FZP device does not rely on sense amplifiers in the product term word line, so it does not have the high offset current associated with that type of structure. The Idd/Freq curve passes very nearly through the axis intersection, while competing parts draw a significant amount of current while just 'idling' at static or low clock frequencies. This provides FZP users with a very large ratiometric advantage at low frequencies; the typical power consumption of the CoolRunner part is 1/1000 that of any other CPLD at quiescent.
At higher maximum clock frequencies, the FZP technology allows FZP CPLD's to operate while drawing only 1/2 to 1/3 the power of competing devices.
Some competitors may be able to place their CPLDs in a power reduced 'non-turbo mode'. Although their parts consume less power, this also bandwidth limits their devices. At that bandwidth limit the FZP CPLDs draw less power; for the same amount of power, the FZP devices deliver twice the bandwidth. CoolRunner CPLDs deliver high speed and low power operation without compromise, while providing a deterministic solution to designs with critical timing requirements. 40
PZ5032 20 20 40 60 80
100
120
140
160
180
Frequency (MHz.)
Zero standby
current

17. CPLD ‘MPG’ Comparison: Mhz / mA
2.5E+12
2.2E+12
Power efficiency calculated from
vendors datasheet values
(1/Tpd) / mA Icc
2.0E+12
1.5E+12
1.0E+12
If power use could be represented in a format similar to miles per gallon, we might most closely represent this in terms of MHz per mA.
This slide graphically shows the difference between the CoolRunner CPLD and other competing devices. Each CPLD’s power efficiency is calculated by taking the inverse of its propagation delay, and dividing that value by the quiescent current required to support that device in full bandwidth mode as it waits for a logic level transition.
Note that the Y axis scale is not linear, and that the CoolRunner devices lead the group by almost three orders of magnitude.
5.0E+11
3.3E+09
2.4E+09
1.9E+09
5.3E+08
1.1E+09
3.3E+09
4.0E+09
0.0E+00
PZ5032
Altera
AMD
Atmel
Cypress
Lattice
Lattice
Xilinx
XC9536
7032
Mach111
ATF1500
371
1016E
2032 25

18. Introducing the Micro BGA
Enhanced Clocking Architecture w/ ISP
3 volt devices on 0.35u process (5 Volt tolerant)
Tpd of 7.5 ns
Static current of < 100uA
56 ball LFBGA package provides 44 I/O’s
0.058 square inch footprint!
Fast Zero Power technology enables the use of very small packages with the CoolRunner silicon. Two devices that have benefited from this capability are the 22V10, which is available in a TSSOP package, and the 64 macrocell AS device which can no be had in a LFBGA (Low profile Fine pitch Ball Grid Array) package.
The 64 macrocell device in the uBGA package is a full bandwidth CPLD, capable of providing Tpd's of 7.5ns.
This revolutionary package provides an 86% board area savings over the standard 44 pin tqfp package!

19. Real Life CoolRunner Story …..More than just battery life
Wireless spread spectrum transmitter
Customer wanted lower power for noise reduction.
Previous solution was two competing 64 macrocell devices per card
Cabinet contained several cards
Switching to CoolRunner saved customer power and money
Efficient XPLA architecture replaced competitive 64 macrocell devices with 32 macrocell devices, cutting cost by almost half
Power savings reported by customer (from replacing only the CPLDs!):
Saving power is not just about prolonging battery life. Many customers are realizing the virtues of reducing the power required by systems. Here are some of the hidden benefits obtained by using low power components:
1) When the power in a system decreases, lower activation energy means that products are more reliable.
2) Self heating of components can cause them to run at temperatures for which they were not qualified. If a commercial part self-heats to 80 deg C, it no longer has characteristics that are guaranteed by its manufacturer.
3) Peripheral components such as power supplies, connectors, and cabling may be downsized; other ancillary devices such as cooling fans and heat sinks may be eliminated entirely. Parts may be placed closer together on PCBs, circuit boards can be populated on both sides, boards may be placed closer together in a rack, and enclosure volumes may be decreased when thermal emissions are minimized.
All of these items result in direct cost savings or risk reduction. Low power is not just about increasing battery life!

20. Software Support
CoolRunner devices are supported by a complete suite of development tools, both proprietary and third party. For designers who already have access to tools such as Orcad, Viewlogic, Synplicity, Synopsis, or Exemplar, XPLA tools provide an edif interface that is free to customers and supports design flows for all of the XPLA CPLD's.

21. XPLA Software Tools XPLA Professional Features Include:
Schematic, PHDL, Verilog and VHDL design entry
Combine entry modes in single project
Supports all CoolRunner Devices
Features Include:
Graphical simulator included
Functional and AC timing simulation
Dynamic current consumption estimator
Based on simulation
Support EDIF flows through popular 3rd party tools
FZP Exclusive !
Proprietary software tools provided by the CoolRunner group include XPLA Designer XL and XPLA Professional.
XPLA Designer XL is a free tool available on the Philips CPLD website ( This tool allows for PHDL (Philips Hardware Descriptive Language, a subset of ABEL) entry, edif interfacing, tt2 and tdo file importation.
XPLA Designer XL supports all CoolRunner devices, and includes full functional and timing simulators which are based upon an 100K gate asic emulator. This tool also provides both Verilog and VHDL output files for simulation with third party simulators.
XPLA Professional includes all of the features found in the 'XL' tool, and also includes schematic and Verilog entry, and will soon support VHDL design entry.
An added feature of both design tools is the innovative Idd current estimator. This tool removes the labor and guess work from power consumption calculations. A designer enters a stimulus into the simulator and requests an Idd calculation by clicking on a radio button to invoke the process. The average current required during the simulation period is subsequently displayed in a result window when calculations are completed.

22. Conversion of Altera Designs…..
Design Conversion
Import *.tdo file into Pro
Compile and fit design
Use pin editor to create .paf
Refit to new pin out
ISP Tool Can Interface to Altera Byte Blaster!
ISP tool auto detects cable type
Preserve customer hardware while stealing socket!
Both XPLA Designer XL and XPLA Pro provide an easy interface for converting Altera Designs. If a customer provides a *.tdo file (a flattened optimized Max+ file that can be selected under 'processing options') and a pin list, most design conversions take less than 10 minutes to perform.
The *.tdo file may be imported directly into XL or Pro as an input file; this file automatically gets translated by the software tool into a *.phd file.
If a customer has an Altera design that they are using the Altera Byte Blaster cable to download to, the new XPLA ISP tool can remap the parallel port driver to 'talk' to the Byte Blaster cable. This will allow a customer to use Altera's cable connected to an Altera ISP header, to talk to a CoolRunner device.
It's easy to convert Altera sockets for CoolRunner evaluation!

23. 22V10 Part Number Cross Reference
P3Z22V10(t)speed,package > XCR22LV10-speed,package(t)
P5Z22V10(t)speed,package >XCR22V10-speed,package(t)
Speed Speed
D 10ns
B 15ns
Package Package
A (28 PLCC) PC
D (24 SO Low profile) SO
DH (24 TSSOP) VO
7 7ns
Note t : Temp range-> Philips uses a dash for commercial, I for industrial
Xilinx uses a C for commercial, I for industrial

24. CoolRunner 22V10 Part Numbering
PZ = Coolrunner Zero Power
x = Supply Voltage
3 = 3.3 volts
5 = 5.0 volts
k = Operating Temperature
- = Commercial
I = Industrial
z = Speed Grade (tPD)
7 = 7.5 ns
D = 10 ns
B = 15 ns
YY = Package Designator
A = 28 PLCC
D = 24 SOL
DH = 24 TSSOP
PxZ22V10kzYY

25. XPLA Original/Enhanced Part Number Cross Reference
PZ5064t,speed,package => XCR5064q-speed,package,t
Speed => Speed
Speeds match 1 for 1 (i.e. 10ns = 10ns)
Package Package
A44 PC44
A68 PC68
A84 PC84
BB1 PQ100
BB2 PQ160
BC VQ44
BE TQ128
BP VQ100
Note q: Process -> C for 0.50u Enhanced, A for 0.35u Enhanced
Note t : Temp range-> Philips uses a dash for commercial, I for industrial Original parts
Philips uses a C for commercial, N for industrial Enhanced (.5u) and XPLA2
parts Philips uses a A for commercial, D for industrial Enhanced (.35u) parts
Xilinx uses a C for commercial, I for industrial

26. CoolRunner CPLD Part Numbering
k = Temp / Architecture / Process Tech.
- = Comm. / XPLA / 0.5u
I = Ind. / XPLA / 0.5u
C = Comm. / XPLAEnhanced / 0.5u
N = Ind. / XPLAEnhanced / 0.5u
A = Comm. / XPLAEnhanced / 0.35u
D = Ind. / XPLAEnhanced / 0.35u
yyy = Macrocell Count
PZ = CoolRunner Zero Power
PZxyyykSzzYYY
x = Supply Voltage
3 = 3.3 volts
5 = 5.0 volts
YYY = Package Designator
A44 = 44 PLCC A68 = 68 PLCC
A84 = 84 PLCC BB1 = 100 PQFP
BB2 = 160 PQFP BC = 44 TQFP
BE = 128 LQFP BP = 100 TQFP
BE = 160 LQFP EB = 492 PBGA
EB = 256 PBGA EC = 56 LFBGA
S = ISP Device (if S is present)
zz = Speed Grade (tPD)
6 = 6 ns 7 = 7.5 ns
8 = 8 ns 10 = 10 ns
12 = 12 ns 15 = 15 ns

27. CoolPLD Technical Support
How to contact us
Phone:
1-888-CoolPLD or
FAX:
Website:
Address:
Philips CPLD Applications Group
9201 Pan American Freeway NE
M/S- 08
Albuquerque, NM 87113
Additional information about this presentation or any other XPLA PLD question may be directed to the applications and marketing group in Albuquerque, NM. 40