NUMERICAL TECHNOLOGIES, INC. Assessing Technology tradeoffs for 65nm logic circuits D Pramanik, M Cote, K Beaudette Numerical Technologies Inc Valery Axelrad Sequoia Design Systems D Pramanik, M Cote, K Beaudette Numerical Technologies Inc Valery Axelrad Sequoia Design Systems

NUMERICAL TECHNOLOGIES, INC. SPIE /27/03 INTRODUCTION  At the 65nm node interaction between process and design can lead to manufacturability crisis  Methodology for assessing tradeoffs between device, circuit and process limits  Use simulation tools to investigate different scenarios for optimum tradeoffs  Electrical and Physical simulations  At the 65nm node interaction between process and design can lead to manufacturability crisis  Methodology for assessing tradeoffs between device, circuit and process limits  Use simulation tools to investigate different scenarios for optimum tradeoffs  Electrical and Physical simulations

NUMERICAL TECHNOLOGIES, INC. SPIE /27/03 Technology variants  Every Technology node has variants to address different market segment needs  Transistors with different parameters are offered based on application needs  Device specifications should drive manufacturability requirements that impact overall costs  One size does not fit all !!  Every Technology node has variants to address different market segment needs  Transistors with different parameters are offered based on application needs  Device specifications should drive manufacturability requirements that impact overall costs  One size does not fit all !!

NUMERICAL TECHNOLOGIES, INC. SPIE /27/03 High Volume Market segments  Low Power (Cellphones/PDA)  Low operating voltage(<1V)  Low operating frequency (<200MHz)  High density  Low active and standby current  Low cost  High Performance (PC/Server/Graphics )  Nominal operating voltage  High operating frequency (>2GHz)  High density  Low Power (Cellphones/PDA)  Low operating voltage(<1V)  Low operating frequency (<200MHz)  High density  Low active and standby current  Low cost  High Performance (PC/Server/Graphics )  Nominal operating voltage  High operating frequency (>2GHz)  High density

NUMERICAL TECHNOLOGIES, INC. SPIE /27/03 Technology Elements Cell Chip Row Block MOSFET

NUMERICAL TECHNOLOGIES, INC. SPIE /27/03 Design flow Architectural Design Synthesis Floorplanning Place and route LVS, DRC, Extract OPC Phase Shifting Silicon Verification SubW Libs. OPC Phase Shifting Silicon Verification Final Analysis & Verification Silicon Simulation Device Models Design rules Functional specs RTL design Silicon Verification Device Simulation

NUMERICAL TECHNOLOGIES, INC. SPIE /27/03 Key formulas Lithography Min Pitch = k 1 /NA DOF = k 2 /NA 2 Lithography Min Pitch = k 1 /NA DOF = k 2 /NA 2  V dd - Supply Voltage  L - Gate length  W - Gate width  C ox - Gate capacitance  V th - Threshold voltage  I on - Fully on current  I off - Off state current Device I on = v sat W C ox (V dd - V dsat ) V dsat when L I off = exp(-V th /S) where S= 80mV/decade Circuit Delay time = C l V dd /I on; C l - avg load capacitance Dynamic power = nC l V dd 2 f n - avg number of switching events

NUMERICAL TECHNOLOGIES, INC. SPIE /27/03 Device simulation Electrical Parameters  V dd - Supply Voltage  L - Gate length  W - Gate width  t ox - Oxide thickness  x j – Junction depth  I on - Fully on current  I off - Off state current L Spacer xjxj Transistor cross-section Gate Source Drain t ox

NUMERICAL TECHNOLOGIES, INC. SPIE /27/03 Device currents vs L TypeV dd (V) L (nm) I on (ma/  m) I off (A/  m) High Performance Short E E E-10 Low Power0.925-Short E E E-11

NUMERICAL TECHNOLOGIES, INC. SPIE /27/03 Device Characteristics Hi Perf Lo Pwr Ion vs Ioff characteristics for device technology Gate oxide Lo Pwr - 16  Hi Perf - 13  Ion vs Ioff characteristics for device technology Gate oxide Lo Pwr - 16  Hi Perf - 13  Off state leakage vs Gate length for both device technologies Hi Perf Lo Pwr

NUMERICAL TECHNOLOGIES, INC. SPIE /27/03 Electrical criteria #CD (nm) Aerial Image contours overlaid on drawn features showing CD variation along length of gate. CD at listed sites shown in table. Avg CD (excluding 4) = 61nm Use OPC to bring avg CD back to 65nm Active 65nm

NUMERICAL TECHNOLOGIES, INC. SPIE /27/03 Cell generation  Technology file -process design rules and recommended rules  Define architecture (cell height, power rails etc)  Input circuit netlist  Cell placed, routed and compacted  View completed cell and if necessary modify, layout and re-compact  Technology file -process design rules and recommended rules  Define architecture (cell height, power rails etc)  Input circuit netlist  Cell placed, routed and compacted  View completed cell and if necessary modify, layout and re-compact

NUMERICAL TECHNOLOGIES, INC. SPIE /27/03 Same function ;Different Drive And 2X4 And 2X0

NUMERICAL TECHNOLOGIES, INC. SPIE /27/03 Cell placement & Circuit Timing tgtg titi A B Timing delay between A and B is the sum of delays through individual cells(t g ) and across interconnects (t i )

NUMERICAL TECHNOLOGIES, INC. SPIE /27/03 Lithography choices with 193nm Att PSMStrong Phase shiftLayout Best contrast and DOF with Strong Phase shift NA 0.85 OAI

NUMERICAL TECHNOLOGIES, INC. SPIE /27/03 FullPhase layer generation Original Active and Poly layers Trim layer Phase shift layers

NUMERICAL TECHNOLOGIES, INC. SPIE /27/03 Aerial Image using 193nm NA = 0.75; sigma=0.4; dose = 3X NA = 0.75; sigma=0.4; dose = 1X

NUMERICAL TECHNOLOGIES, INC. SPIE /27/03 Manufacturability analysis Analysis of simulated images show following areas of improvement  Process  Improved Depth of Focus (DOF) by changing poly pitch from 160nm to 180nm  Better CD control - less OPC  Electrical  Poly contact pads shrink substantially leading to high contact resistance.  Poly-contact overlap improved by going to larger contacts and larger poly extensions Analysis of simulated images show following areas of improvement  Process  Improved Depth of Focus (DOF) by changing poly pitch from 160nm to 180nm  Better CD control - less OPC  Electrical  Poly contact pads shrink substantially leading to high contact resistance.  Poly-contact overlap improved by going to larger contacts and larger poly extensions

NUMERICAL TECHNOLOGIES, INC. SPIE /27/03 Impact of Design rules Poly pitch – 160nm Contacts – 80nm Contact extension – 35nm Poly pitch – 180nm Contacts – 90nm Contact extension – 45nm

NUMERICAL TECHNOLOGIES, INC. SPIE /27/03 Simulation of new cells Defocus 100nm Defocus 0nm Cell with larger poly pitch and larger contact pads

NUMERICAL TECHNOLOGIES, INC. SPIE /27/03 Summary  Simulation of device characteristics allow the circuit impact of lithography variations to be assessed  Strong Alt PSM needed for printing poly features using 193nm  Automated layout tools allow tradeoff between layout design rules, circuit density and manufacturability  Simulation of device characteristics allow the circuit impact of lithography variations to be assessed  Strong Alt PSM needed for printing poly features using 193nm  Automated layout tools allow tradeoff between layout design rules, circuit density and manufacturability