1. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. Power MOSFET (3) 2013. 1. 10. SD Lab. SOGANG Univ. BYUNGSOO KIM

2. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. Contents 1.Power U-MOSFET On-Resistance 2. Power U-MOSFET Cell Optimization 3. Device Capacitances

3. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 1. Power U-MOSFET On-Resistance The exception of the JFET region resistance - a significant reduction of the overall specific on-resistance - much smaller cell pitch =>reduction of the specific resistance The total on resistance:

4. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 1. Power U-MOSFET On-Resistance 1.1 Source Contact Resistance The contact resistance: The specific contact resistance: The cell width: Ex)

5. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 1. Power U-MOSFET On-Resistance 1.2 Source Region Resistance

6. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 1. Power U-MOSFET On-Resistance 1.3 Channel Resistance channels formed on both of the vertical sidewalls of the trench-gate structure

7. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 1. Power U-MOSFET On-Resistance 1.4 Accumulation Resistance

8. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 1. Power U-MOSFET On-Resistance 1.5 Drift Region Resistance

9. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 1. Power U-MOSFET On-Resistance 1.6 N+ Substrate Resistance

10. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 1. Power U-MOSFET On-Resistance 1.7 Drain Contact Resistance

11. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 1. Power U-MOSFET On-Resistance 1.8 Total On-Resistance

12. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 1. Power U-MOSFET On-Resistance 1.8 Simulation Example

13. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 2. Power U-MOSFET Cell Optimization 2.1 Orthogonal P-Base Contact Structure an increase in the channel density by a factor of 2.5 times resulting in a smaller specific on-resistance A design with a ratio (ZN+/ZP) of 10 provides an adequate design compromise

14. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 2. Power U-MOSFET Cell Optimization 2.1 Orthogonal P-Base Contact Structure

15. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 2. Power U-MOSFET Cell Optimization 2.2 Impact of Breakdown Voltage The breakdown voltage capability - a higher resistivity drift region - larger thickness improvements in the performance of the power U-MOSFET structure - by improving the edge termination design

16. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 2. Power U-MOSFET Cell Optimization 2.3 Ruggedness Improvement the enhanced electric field rounding the bottom of the trenches the enhanced electric field rounding the bottom of the trenches the inclusion of a deep P+ region larger cell pitch increase of the on-resistance

17. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. In practice the switching speed is limited by the device capacitances. the small thickness of the gate oxide - a significant capacitance The rate of switching between the on-state and off-state => determined by The rate of being charged or discharged A role of the capacitance between the drain and the gate electrodes - the drain current and voltage transitions during the switching event 3. Device Capacitances

18. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 3. Device Capacitances 6.1 Basic MOS Capacitance

19. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 3. Device Capacitances

20. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 3. Device Capacitances 6.2 Power VD-MOSFET Structure Capacitances The input (or gate) capacitance of the structure - the overlap of the gate electrode with the N+ source and P-base regions - determined by the oxide capacitance It is common design practice in power VD-MOSFET structures to overlap the source electrode over the gate electrode. - a very thick metal layer (4–10 μm) to reduce its resistance =>an additional input capacitance - a thick (typically 6,000 Å) interelectrode dielectric film (t IEOX )

21. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. The specific input capacitance: The gate–drain (or reverse transfer) capacitance: 3. Device Capacitances

22. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 3. Device Capacitances C SM is decreases with increasing drain bias voltage. The applied drain bias:

23. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 3. Device Capacitances

24. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 3. Device Capacitances The output capacitance (CO) is associated with the capacitance of the junction between the P-base region and the N-drift region. The specific junction capacitance the depletion region thickness at the junction

25. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 3. Device Capacitances 6.3 Power U-MOSFET Structure Capacitances The input (or gate) capacitance - the overlap of the gate electrode with the N+ source and P-base regions along the sidewalls of the trench - determined by the oxide capacitance The formation of a large source metal area - a very thick metal layer (4–10 μm) to reduce its resistance=>an additional input capacitance - a relatively thick (typically 6,000 Å) interelectrode dielectric film (t IEOX )

26. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. The specific input (or gate) capacitance: The input capacitance for the power U-MOSFET is much larger than that for the power VD-MOSFET. the reduction of the specific on-resistance with the power UMOSFET structure is attended with an increase in the input gate capacitance. The reduction of the specific input capacitance of the power U-MOSFET - increasing the mesa width - accompanied by an increase in the specific on- resistance 3. Device Capacitances

27. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 3. Device Capacitances much larger than that for the power VDMOSFET greatly reduced when the mesa width is enlarged an increase in the specific on-resistance

28. SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. 3. Device Capacitances the model A - without screening (KS = 0) - a much larger specific output capacitance the model B - a screening factor KS = 0.75 - the extracted values Model A: Model B: