1. Design For Manufacturability in Nanometer Era
Class Presentation:
Design For Manufacturability in Nanometer Era
ADVANCED VLSI COURSE
Supervisor: DR. Fakhraei
Provided by
Negar Shoa-azar

2. Introduction:
With each new process node, additional defect mechanisms appear and hinder the ability to achieve desired yield. The trend toward declining yields has created resurgence in the application of design for manufacturing (DFM) methodologies.

3. DFM
The design methodology called Design for Manufacturability (DFM) includes a set of techniques to modify the design of ICs in order to make them more manufacturable, i.e. to improve their functional yield, parametric yield, or reliability.

4. Yield Loss Mechanisms Yield loss mechanisms are :
Random Yield Loss Mechanisms.
Design Systematic Yield Loss Mechanisms.
Parametric Yield Loss Mechanisms.

5. Random Yield Loss Mechanisms
Random defects and contaminants are among the most well known and deeply studied yield loss mechanisms. They cause electrical feature shorts and opens such as, for example:
metal shorts and opens due to particle defects.
At larger technologies, random defects are the dominant yield loss mechanism.

6. Random Yield Loss Mechanisms
Figure.1: metal shorts and opens[1].

7. Systematic Yield Loss Mechanisms
Systematic yield issues are a result of interaction between the layout and process variations. These include chemical variations in materials; mechanical variations in CMP, optical variations in lithography and plasma variations in etch. Some examples of systematic defects are: planarity (the difference in metal heights for a given area on a design).

8. Systematic Yield Loss Mechanisms
Figure. 2: failure mode in sparse via2/via1[1].

9. Systematic Yield Loss: Printability
Figure. 3: failures due printability issues[1].

10. Parametric Yield Loss Mechanisms
The biggest impact in nanometer designs is attributed to parametric yield loss. This is when all elements of a chip are functioning, but timing or other electrical requirements, such as power, are not to specification. Parametric defects became an issue at 180nm, grew dramatically at 130nm, and are of significant concern in 90nm designs.

11. Parametric Yield Loss Mechanisms
M1-necking
M1 pull-back
Figure. 4: Metal1 necking and pull-back failure[1].

12. Product Yield Modeling Accuracy
Figure. 5: Yield prediction[1].
Yield modeling accuracy is excellent
Error represents unidentified yield loss mechanisms or lack of yield model[1].

13. Three Main Components of The DFM Methodology
Modification of the IP library in order to include variants of the basic standard cell implementations to address different yield loss mechanisms for the same logic functionality and driving strength.
Data file containing the accurate characterization of the yield attributes of the library.
Extension of the physical synthesis tools to incorporate yield in the logic optimization cost function. Since the size of logic blocks is often dominated by routing, the synthesis tool can exploit placement and timing slacks to optimize for yield without increasing block size or delay.

14. The Evolution of Product Yields
Random defects are no longer the dominant yield loss mechanism.
Yields are limited by design features[1]

15. Figure. 5: Measured good die per wafer improvement for 5 ICs with the
And the Silicon Says…
Figure. 5: Measured good die per wafer improvement for 5 ICs with the
proposed DFM method.

16. Conclusion
Model-based, proactive DFM philosophy consists in the development of accurate, silicon verified YLM models that can evaluate the relative impact of each YLM and assess trade-offs. These models are then integrated in the design tool’s cost function along with other design objectives such as speed, power and signal integrity functions. Design tools are thus able to exploit the design locality property of design systematic YLM as well as global random YLM to achieve the optimal manufacturability compatible with the actual IC design specifications.

17. References:
John Kibarian, et Al. “Design For manufacturability in Nanometer Era: System Implementation and Silicon Results”, Proceedings of ISSCC, San Francisco, CA, Feb 2005
Carlo Guardiani, et Al. “An Effective DFM Strategy Requires Accurate Process and IP Pre-Characterization” , DAC, Anaheim, CA, Jun. 2005

18. Thanks
For Your Attention