1. Toward a Methodology for Manufacturability-Driven Design Rule Exploration Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, and Jie Yang Univ. of Michigan, Ann Arbor Univ. of California, San Diego Advanced Micro Devices

2. Outline Introduction Introduction Motivation of the restrictive design rule (RDR) approach Motivation of the restrictive design rule (RDR) approach RDR embedded design flow RDR embedded design flow Evaluation metrics Evaluation metrics Experimental results Experimental results Conclusions and future work Conclusions and future work

3. Introduction Projected gate CD control in sub-wavelength lithography regime (ITRS 2003) Projected gate CD control in sub-wavelength lithography regime (ITRS 2003) Year2001200420072009 Technology node MPU gate length (nm) Gate CD control (3σ) (nm) 130nm905.390nm533.7565nm35 2.550nm28 2 MPU pitch (nm) Wavelength (λ) (nm) 300248180193130193100 157 (?) –Manufacturable solutions are not known for italicized numbers –Intel may not use 157nm at 50nm technology node

4. Introduction (Cont.) Trends in Mask Cost Trends in Mask Cost –Mask data preparation is a serious bottleneck due to the heavily applied RET Figure count explodes as dimensions shrink Figure count explodes as dimensions shrink Data volume for a single mask layer can approach 200GB Data volume for a single mask layer can approach 200GB

5. Introduction (Cont.) Trends in Mask Cost (Cont.) Trends in Mask Cost (Cont.) –Mask writing time increases from a few days to over a month –Mask set cost increases at an accelerated rate with RET application as the primary driver –ASIC users turn to FPGAs due to high mask cost on low volume designs

6. Outline  Introduction Motivation of the restrictive design rule (RDR) approach Motivation of the restrictive design rule (RDR) approach RDR embedded design flow RDR embedded design flow Evaluation metrics Evaluation metrics Experimental results Experimental results Conclusions and future work Conclusions and future work

7. Motivation of RDR RETs need to become part of a cohesive design flow in which libraries and layouts are optimized directly based on conflicts discovered by the RET tool, no longer a post-layout procedure RETs need to become part of a cohesive design flow in which libraries and layouts are optimized directly based on conflicts discovered by the RET tool, no longer a post-layout procedure More conservative design rules or restricted design rules (RDRs) seek to push the manufacturability and performance tradeoff more in favor of the manufacturing side More conservative design rules or restricted design rules (RDRs) seek to push the manufacturability and performance tradeoff more in favor of the manufacturing side Apply RDR within ASIC design methodology Apply RDR within ASIC design methodology

8. Outline  Introduction  Motivation of the restrictive design rule (RDR) approach RDR embedded design flow RDR embedded design flow Evaluation metrics Evaluation metrics Experimental results Experimental results Conclusions and future work Conclusions and future work

9. RDR Embedded Design Flow

10. RDR Candidates Bentgate “ on ” as baseline (1) Bentgate “ on ” as baseline (1) –Bentgate line width (5) Bentgate “ off ” Bentgate “ off ” –Poly to poly spacing (2) –Poly to diffusion spacing (3) –Poly end extension (4) (3) (2) (4) (5) (1)

11. Value Ranges of RDR The parentheses contain the corresponding labels in all figures Use IBM 0.13μm technology as “default” Use IBM 0.13μm technology as “default” Guideline Guideline –Start from the most “free” design rule set, i.e., for best performance in delay & area – “bentgate on” as baseline –Create more conservative design rules Only one rule differs from “Default” rule set Only one rule differs from “Default” rule set Moving to more conservative direction, e.g. increasing poly to poly spacing, line width, etc. Moving to more conservative direction, e.g. increasing poly to poly spacing, line width, etc.

12. Value Ranges of RDR (Cont.) We use edge placement errors (EPEs) as a quantifying metric to determine value range We use edge placement errors (EPEs) as a quantifying metric to determine value range –Measure how closely a printed feature actually reflects the corresponding designed feature –Defined as the distance between the edges of printed image and drawn feature (positive value indicates printed image outside of drawn feature boundary while negative value indicates it ’ s inside) EPE>0 EPE<0 EPE>0 EPE<0 EPE>0 EPE<0 (a)(b)

13. Value Ranges of RDR (Cont.) Deter mine the “ forbidden pitch ” Deter mine the “ forbidden pitch ” –Define 0.42μm to 0.72μm as the forbidden pitch range according to simulation results

14. Outline  Introduction  Motivation of the restrictive design rule (RDR) approach  RDR embedded design flow Evaluation metrics Evaluation metrics Experimental results Experimental results Conclusions and future work Conclusions and future work

15. Evaluation Metrics For manufacturability: EPE and average CD For manufacturability: EPE and average CD –EPEs to measure the effectiveness of OPC Goal is to achieve a tight EPE distribution with mean around zero Goal is to achieve a tight EPE distribution with mean around zero –Using average CD to compensate for the limitation of EPE The EPE distributions can not correctly reflect CD The EPE distributions can not correctly reflect CD Use average gate-length calculated from a printed non-uniform gate area for further evaluation Use average gate-length calculated from a printed non-uniform gate area for further evaluation For OPC cost: MEBES data volume For OPC cost: MEBES data volume –MEBES is the standard mask writer format The explosion of MEBES data volume due to RETs has made mask data preparation a serious bottleneck. The explosion of MEBES data volume due to RETs has made mask data preparation a serious bottleneck. It shows the complexity of OPC layer and reflects the mask cost It shows the complexity of OPC layer and reflects the mask cost Mask OPC Fracture

16. Outline  Introduction  Motivation of the restrictive design rule (RDR) approach  RDR embedded design flow  Evaluation metrics Experimental results Experimental results Conclusions and future work Conclusions and future work

17. Experimental Results Impact of defocus on maximum EPE levels vs. RDRs Impact of defocus on maximum EPE levels vs. RDRs

18. Experimental Results Impact of defocus on CD distribution (circuit: c7552) Impact of defocus on CD distribution (circuit: c7552) Defocus 0 0.1 (µm) 0.2 (µm) 0.3 (µm) RDRMeanσMeanσMeanσMeanσ sp_20147.27.79140.27.98138.38.08136.27.99 sp_24147.07.79141.07.91138.17.94136.19.54 sp_28146.77.97139.87.84137.77.54134.88.67 pdsp_10147.18.23140.38.16138.28.36135.89.03 pdsp_12147.18.48141.28.23137.98.44135.58.55 povg_34140.28.27138.98.13138.88.90135.19.10 povg_40140.59.58142.59.25139.29.03136.433.7 bentgate146.98.05139.17.60135.77.41132.67.97 bent_w14147.07.80139.37.36135.47.13132.97.08

19. Experimental Results Impact of defocus on functional yield for a fixed 10% L gate variation (circuit: c7552) Impact of defocus on functional yield for a fixed 10% L gate variation (circuit: c7552)

20. Experimental Results Scattering bars (or sub-resolution assist features) (circuit: c7552) Scattering bars (or sub-resolution assist features) (circuit: c7552)

21. Experimental Results Approach of the single pitch RDR (circuit: c7552) Approach of the single pitch RDR (circuit: c7552) –Single pitch, single orientation –Poly pitch larger than default value to allow contact be inserted –Pseudo single pitch (97.6% fixed at a single value) –AOI, OAI cells are excluded –With SRAFs tuned for the single pitch library at 0.1µm defocus

22. Experimental Results Circuit performance analysis Circuit performance analysis

23. Experimental Results Tradeoff between functional yield at 10% EPE tolerance and mask cost with loose OPC for corner correction (circuit: c7552) Tradeoff between functional yield at 10% EPE tolerance and mask cost with loose OPC for corner correction (circuit: c7552) RDR Slightly Conservative Very Conservative YieldMEBESYieldMEBES sp_201.000.980.810.91 sp_241.000.970.800.90 sp_281.000.990.780.94 pdsp_101.000.980.810.86 pdsp_121.000.980.820.95 povg_341.000.980.910.93 povg_401.000.980.910.97 bentgate1.000.990.840.97 bent_w140.991.000.840.92

24. Conclusions and Future Work Restrictive design rules can result in more robust and cost-effective circuits without sacrificing performance Restrictive design rules can result in more robust and cost-effective circuits without sacrificing performance Data volume reduction on the order of 20-30% relative to baseline rule set Data volume reduction on the order of 20-30% relative to baseline rule set Worst-case EPE reduction nearly 50% with small penalty on performance Worst-case EPE reduction nearly 50% with small penalty on performance RDR sets can be formulated to support sub- wavelength lithography by providing substantial cost reductions with negligible performance tradeoff RDR sets can be formulated to support sub- wavelength lithography by providing substantial cost reductions with negligible performance tradeoff

25. Conclusions and Future Work Multi-layer design rules Multi-layer design rules –Metal design rules Besides poly, OPC is also heavily applied on metal. Metal design rules are promising candidates for RDRs Besides poly, OPC is also heavily applied on metal. Metal design rules are promising candidates for RDRs –Contact design rules A great number of correcting features are inserted to maintain the fidelity of the layer covering the contact while the goal should be obtain enough overlap area A great number of correcting features are inserted to maintain the fidelity of the layer covering the contact while the goal should be obtain enough overlap area E.g., avoid contact very close to metal line end may reduce both the OPC cost on metal and the possibility for an open fault E.g., avoid contact very close to metal line end may reduce both the OPC cost on metal and the possibility for an open fault Performance analysis for post-OPC Performance analysis for post-OPC Reduce correction cost on field poly whenever possible Reduce correction cost on field poly whenever possible