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Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-1 Lecture 10 Wire and Via Jan. 27, 2003.

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Presentation on theme: "Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-1 Lecture 10 Wire and Via Jan. 27, 2003."— Presentation transcript:

1 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-1 Lecture 10 Wire and Via Jan. 27, 2003

2 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-2 Topics n Wire and via structures. n Wire parasitics and resistance. n Transistor parasitics and resistance.

3 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-3 Wires and vias p-tub poly n+ metal 1 metal 3 metal 2 vias

4 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-4 Metal migration n Current-carrying capacity of metal wire depends on cross-section. Height is fixed, so width determines current limit. n Metal migration: when current is too high, electron flow pushes around metal grains. Higher resistance increases metal migration, leading to destruction of wire.

5 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-5 Metal migration problems and solutions n Marginal wires will fail after a small operating period—infant mortality. n Normal wires must be sized to accomodate maximum current flow: I max = 1.5 mA/  m of metal width. n Mainly applies to V DD /V SS lines.

6 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-6 Diffusion wire capacitance n Capacitances formed by p-n junctions: n+ (N D ) depletion region substrate (N A ) bottomwall capacitance sidewall capacitances

7 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-7 Depletion region capacitance n Zero-bias depletion capacitance: –C j0 =  si /x d. n Depletion region width: –x d0 = sqrt[(1/N A + 1/N D )2  si V bi /q]. n Junction capacitance is function of voltage across junction: –C j (V r ) = C j0 /sqrt(1 + V r /V bi )

8 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-8 Poly/metal wire capacitance n Two components: –parallel plate; –fringe. plate fringe

9 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-9 Metal coupling capacitances n Can couple to adjacent wires on same layer, wires on above/below layers: metal 2 metal 1

10 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-10 Example: parasitic capacitance measurement n n-diffusion: bottomwall=2 fF, sidewall=2 fF. n metal: plate=0.15 fF, fringe=0.72 fF. 3  m 0.75  m 1  m 1.5  m 2.5  m

11 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-11 Wire resistance n Resistance of any size square is constant:

12 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-12 Mean-time-to-failure n MTF for metal wires = time required for 50% of wires to fail. n Depends on current density: –proportional to j -n e Q/kT –j is current density –n is constant between 1 and 3 –Q is diffusion activation energy

13 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-13 Skin effect n At low frequencies, most of copper conductor’s cross section carries current. n As frequency increases, current moves to skin of conductor. –Back EMF induces counter-current in body of conductor. n Skin effect most important at gigahertz frequencies.

14 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-14 Effect on resistance n Low frequency resistance of wire: –R dc = 1/  wt n High frequency resistance with skin effect: –R hf = 1/2  (w + t) n Resistance per unit length: –R ac = sqrt(R dc 2 +  R hf  2  Typically  = 1.2.

15 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-15 Review n Current characteristics n Capacitance n Wire and via (tub tie)

16 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-16 Lectures 11 Design Rule and Stick Diagram Jan. 29, 2003

17 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-17 Topics n Design rules and fabrication. n Color codes and Stick diagrams.

18 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-18 Why we need design rules n Masks are tooling for manufacturing. n Manufacturing processes have inherent limitations in accuracy. n Design rules specify geometry of masks which will provide reasonable yields. n Design rules are determined by experience.

19 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-19 Manufacturing problems n Photoresist shrinkage, tearing. n Variations in material deposition. n Variations in temperature. n Variations in oxide thickness. n Impurities. n Variations between lots. n Variations across a wafer.

20 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-20 Transistor problems n Varaiations in threshold voltage: –oxide thickness; –ion implanatation; –poly variations. n Changes in source/drain diffusion overlap. n Variations in substrate.

21 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-21 Wiring problems n Diffusion: changes in doping -> variations in resistance, capacitance. n Poly, metal: variations in height, width -> variations in resistance, capacitance. n Shorts and opens:

22 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-22 Oxide problems n Variations in height. n Lack of planarity -> step coverage. metal 1 metal 2

23 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-23 Via problems n Via may not be cut all the way through. n Undesize via has too much resistance. n Via may be too large and create short.

24 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-24 MOSIS SCMOS design rules n Designed to scale across a wide range of technologies. n Designed to support multiple vendors. n Designed for educational use. n Ergo, fairly conservative.

25 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-25 and design rules is the size of a minimum feature. Specifying particularizes the scalable rules. Parasitics are generally not specified in  units 

26 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-26 Wires metal 3 6 metal 2 3 metal 1 3 pdiff/ndiff 3 poly 2

27 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-27 Transistors 2 3 1 3 2 5

28 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-28 Vias n Types of via: metal1/diff, metal1/poly, metal1/metal2. 4 1 4 2

29 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-29 Metal 3 via n Type: metal3/metal2. n Rules: –cut: 3 x 3 –overlap by metal2: 1 –minimum spacing: 3 –minimum spacing to via1: 2

30 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-30 Tub tie 4 1

31 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-31 Spacings n Diffusion/diffusion: 3 n Poly/poly: 2 n Poly/diffusion: 1 n Via/via: 2 n Metal1/metal1: 3 n Metal2/metal2: 4 n Metal3/metal3: 4

32 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-32 Overglass n Cut in passivation layer. Minimum bonding pad: 100  m. n Pad overlap of glass opening: 6 n Minimum pad spacing to unrelated metal2/3: 30 n Minimum pad spacing to unrelated metal1, poly, active: 15

33 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-33 Example 1

34 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-34 Color codes n PolySilicon -- Red n Ndiffusion -- Green n Pdiffusion -- Brown n Metal1 -- Blue n Metal2 -- Purple n Contacts/Via -- Black “X” n Nsubstrate Contact -- Green “X” n Psubstrate Contact -- Brown “X”

35 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-35 Stick diagrams n A stick diagram is a cartoon of a layout. n Does show all components/vias (except possibly tub ties), relative placement. n Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.

36 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-36 Stick layers metal 3 metal 2 metal 1 poly ndiff pdiff

37 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-37 Dynamic latch stick diagram VDD in VSS phi phi’ out

38 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-38 Sticks design of multiplexer n Start with NAND gate:

39 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-39 NAND sticks VDD a VSS out b

40 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-40 One-bit mux sticks VDD VSS N1 (NAND) select’ out a b N1 (NAND) out a b N1 (NAND) out a b select aiai bibi

41 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-41 3-bit mux sticks m2(one-bit-mux) select’selectVDD VSS oioi aiai bibi m2(one-bit-mux) select’selectVDD VSS oioi aiai bibi m2(one-bit-mux) select’selectVDD VSS oioi aiai bibi select’ select a2a2 b2b2 a1a1 b1b1 a0a0 b0b0 o2o2 o1o1 o0o0

42 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-42 Layout design and analysis tools n Layout editors are interactive tools. n Design rule checkers are generally batch--- identify DRC errors on the layout. n Circuit extractors extract the netlist from the layout. n Connectivity verification systems (CVS) compare extracted and original netlists.

43 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-43 Automatic layout n Cell generators (macrocell generators) create optimized layouts for ALUs, etc. n Standard cell/sea-of-gates layout creates layout from predesigned cells + custom routing. –Sea-of-gates allows routing over the cell.

44 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-44 Standard cell layout routing area

45 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-45 Lecture 12 Cadence Tutorial Jan. 31, 2003

46 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-46 Lab 1 Cadence Tutorial

47 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-47 Assignment 1 Questions: 2.1, 2.2, 2.5, 2.6, 2.7, 2.9 Due date: Feb. 12, 2003 12:00 pm Drop off: EC 2135

48 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-48 Lecture 13 Chapter 2 Review Feb. 3, 2003

49 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-49 n Digital characteristics of transistor n Current characteristics of transistor n Capacitance of transistor n Wire and via n Design rules and stick diagram Review of Chapter 2

50 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-50 Contents of the Course ASICFPGA n Transistor and Layout n Gate and Schematic n Systems and VHDL/Verilog

51 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-51 Examples

52 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-52

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