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Tutorial on Subwavelength Lithography DAC 99
Y. C. (Buno) Pati Numerical Technologies, Inc.
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Agenda Background The SubWavelength Gap SubWavelength Technologies
DAC 99 June 24, 1999 Agenda Background The SubWavelength Gap SubWavelength Technologies Optical proximity correction (OPC) Phase shifting Process modeling Silicon Level Verification Some implications for physical design?
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Optical Lithography Image of circuit patterns projected onto wafer
DAC 99 June 24, 1999 Optical Lithography Image of circuit patterns projected onto wafer Feature size limited by diffraction effects Rayleigh limits Illumination (Wavelength l) Mask Silicon Wafer Resolution q Depth of focus Numerical Aperture:
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Mask Types Bright Field Masks Dark Field Masks
DAC 99 June 24, 1999 Mask Types Bright Field Masks Opaque features defined by chrome Background is transparent Used e.g. for poly, metal, ... Dark Field Masks Transparent features defined Background is opaque (chrome) Used e.g. for contacts, ... Clear areas Opaque (chrome) areas
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Next Generation Lithography Technologies
DAC 99 June 24, 1999 Next Generation Lithography Technologies Extended UV EUV - 13nm wavelength x-rays Electron beams Common characteristics: At least 10 years away Requires significant research and development Requires major infrastructure changes More than 25 years of infrastructure and experience supporting supporting optical lithography
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The SubWavelength™ Gap
DAC 99 June 24, 1999 The SubWavelength™ Gap Lithography Wavelength Silicon Feature Size
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The Impact of SubWavelength Lithography
DAC 99 June 24, 1999 The Impact of SubWavelength Lithography LAYOUT MASK SILICON WAFER Traditional (WSYIWYG) relationship between layout, mask and silicon is no longer valid due to process distortions, OPC, and phase shifting
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Bridging the SubWavelength™ Gap
DAC 99 June 24, 1999 Bridging the SubWavelength™ Gap
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Optical Proximity Correction (OPC)
DAC 99 June 24, 1999 Optical Proximity Correction (OPC) Silicon Image w/o OPC Conventional (no OPC) Corrective modifications to improve process control improve yield improve device performance Original Layout 0.18 mm OPC Layout Silicon Image with OPC
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Phase-Shifting (PSM) Technology
DAC 99 June 24, 1999 Phase-Shifting (PSM) Technology Gate lengths reduced to 0.1 mm Silicon Image w/o PSM Phase modulation used at mask level to reduce feature size improve yield improve device performance Original Layout 0.18 mm Silicon Image with PSM PSM Layout
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0.11mm With Phase Shifting Light Source 180 o phase shifter
DAC 99 June 24, 1999 With Phase Shifting Light Source Mask Opaque 180 o phase shifter Transparent Wafer Without Phase Shifting 0.11mm 0.11 mm silicon features printed using a 0.35 mm nominal process Scanning Electron Micrograph (SEM) courtesy Hewlett Packard Insufficient image contrast to successfully print silicon features
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0.18 micron transistors fabricated with a 0.18 micron process
DAC 99 June 24, 1999 0.18 mm 0.18 micron transistors fabricated with a 0.18 micron process 0.09 mm 0.09 micron transistors fabricated with the same 0.18 micron process and NTI phase shifting technology SEM Courtesy Motorola
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Optical Proximity Correction
DAC 99 June 24, 1999 Optical Proximity Correction Goal: Improve device performance and yield Cosmetic correction complicates mask manufacturing and dramatically increases cost with little benefit OPC is not new, it’s just more complicated than it was before Key issues: Manufacturability Design and verification tools OPC Features Serifs - for corner rounding Hammerheads - for line-end shortening Assists - for CD control Biasing - for CD control
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Approaches to OPC Rule-Based OPC Model-Based OPC
DAC 99 June 24, 1999 Approaches to OPC Rule-Based OPC Apply corrections based on a set of pre-determined rules Fast design time Lower mask complexity Suitable for less “aggressive” designs Model-Based OPC Use process simulation to determine corrections on-line Longer design time Increased mask complexity Suitable for “aggressive” designs
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Phase-Shifting - Background
DAC 99 June 24, 1999 Phase-Shifting - Background Proposed for lithography application in 1982 by Marc Levenson (IBM) Heightened interest in early 90’s Near wavelength - no pressing need Infrastructure, i.e. design automation, mask manufacturing, ... not in place Many different forms of phase-shifting proposed Key issues: Manufacturability Design and verification tools
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Some Forms of Phase-Shifting Masks
DAC 99 June 24, 1999 Some Forms of Phase-Shifting Masks 0 Bright Field Phase-Shifting Single exposure Phase transitions required e.g. 60, 120, 90, 270 Throughput unaffected Limited improvement in process latitude Mask manufacturing difficult Double exposure PSM with 0 and 180 degree phase shifters + binary trim mask Excellent process latitude Decrease in throughput 120 90 270 180 60
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Gate Shrinking and CD Control Using Phase Shifting
DAC 99 June 24, 1999 Gate Shrinking and CD Control Using Phase Shifting Dark Field PSM Prints 0.11 mm lines Original Design Binary Mask (0.20 mm) Prints 0.20 mm line 0.11 mm gates + Poly Active Phase Shifters 180
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Image Formation Using Double Exposure Phase Shifting
DAC 99 June 24, 1999 Image Formation Using Double Exposure Phase Shifting Chrome Mask PSM Combined DUV, NA=0.60, s= 0.50
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Phase Shifting Improves Critical Dimension (CD) Control
DAC 99 June 24, 1999 Phase Shifting Improves Critical Dimension (CD) Control BIM (250 nm L/S ) PSM (150 nm L/ 300 nm S) Line width contours shown for a full wafer (45 fields, 36 measurements per field. Contour interval: 5nm. DUV, NA = 0.42, s = 0.5 (Joint work with Hua-Yu Liu*, HP ULSI Research Laboratories) * Now at Numerical Technologies
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Controlling Silicon Dimensions Phase Shift vs. Binary
DAC 99 June 24, 1999 Controlling Silicon Dimensions Phase Shift vs. Binary DUV, NA=0.57, s=0.40 Phase Shifting Binary Wafer Dimension (mm) 180° 0° X Mask Dimension (mm)
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SubWavelength Infrastructure
DAC 99 June 24, 1999 SubWavelength Infrastructure Production Process Subwavelength Mask FAB Design Physical Design Extraction Verification EDA Software Tools SubWavelength Design Tools Mask Manufacturing Defect Inspection Repair Inspection and Repair Equipment SubWavelength Inspection/Repair Process Optimization Process Simulation and Development Tools SubWavelength Process Development Design Rule Generation
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Phase-shifting Technology Impacts Physical Layout
DAC 99 June 24, 1999 Phase-shifting Technology Impacts Physical Layout Phase conflicts occur when two objects with minimum spacing cannot be assigned contrasting phase Layout designers must ensure that layouts are free of phase conflicts This is analogous to, but not the same as checking design rules 180° 0° Phase Conflict 180° 0° Conflict Eliminated
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SubWavelength Design and Manufacturing Data Flow
DAC 99 June 24, 1999 SubWavelength Design and Manufacturing Data Flow
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Calibrated Process Simulation Models
DAC 99 June 24, 1999 Calibrated Process Simulation Models printed pattern Lithography Process mask process stepper optics photo resist etch calibrated model layout Process Model simulated printed pattern
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Applications of Process Models
DAC 99 June 24, 1999 Applications of Process Models Process Measurements Process Model Calibrator Calibrated Process Model Process Simulation OPC Phase Shifting Inputs Outputs PS & OPC Rule Generation Silicon DRC Si Image Extraction Mask Inspection
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DAC 99 June 24, 1999
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Silicon Verification - Silicon vs. Layout
DAC 99 June 24, 1999 Silicon Verification - Silicon vs. Layout FAIL! PASS ! Physical Silicon Level Verification Verification X Design Layout - DRC ü Silicon - DRC X Layout - LVS ü Silicon - LVS Layout - Timing ü Silicon - Timing X FAIL! Layout Compares silicon to layout Silicon level verification can catch silicon failures prior to commiting to masks and silicon
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Silicon image simulation checks against target, and flags failures
DAC 99 June 24, 1999 How does it work? Silicon image simulation checks against target, and flags failures
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DAC 99 June 24, 1999 Summary SubWavelength technologies are critical to IC manufacturing for the next 7-10 years OPC is a corrective technology Phase shifting is an enabling technology SubWavelength design and manufacturing requires the coordinated interaction of physical design with lithography process, semiconductor equipment, and mask manufacturing Moore’s Law will live on (for now)! ….
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