1. 20-NM CMOS DESIGN

2. 2nd generation strain, 10 metal layers 32/28nm 2010 High-K metal gate
MICROWIND APPLICATION NOTES
Technology node
Year of introduction
Key Innovations
90nm
2003
SOI substrate
65nm
2004
Strain silicon
45nm
2008
2nd generation strain, 10 metal layers
32/28nm
2010
High-K metal gate
20nm
2013
Replacement metal gate, Double patterning, 12 metal layers
14nm
2015
FinFET
> Application Notes

3. 20-NM APPLICATION NOTE
The Joint Development Alliance has released in 2012 a 20-nm technology
Microwind’s 20-nm rule file has been tuned to the JDA 20-nm technology based on available publications

4. MOS CURRENT DRIVE MOS Current drive (mA/µm) This application note 2.0
FinFET for increasing drive current and reducing leakage
High K Metal Gate to increase field effect
MOS
Current drive (mA/µm)
Strain to increase mobility
This application note
High performance
2.0
General Purpose
1.5
Ioff: 100nA/µm
Low power
1.0
10nA
1 nA
0.5
0.0
130 nm
90 nm
65 nm
45 nm
32 nm
20 nm
14 nm
10 nm
Intrinsic performances
Gate material
Technology node
Strain

5. 90nm 45nm 20nm Power -50% -80% 90nm 45nm 20nm SCALE DOWN BENEFITS
Smaller
Faster
Less power consumption
Cheaper (if you fabricate millions)
90nm
45nm
20nm
Power
-50%
-80%
90nm
45nm
20nm

6. SCALE DOWN BENEFITS
Maximum die size
One Core
One core
AMD dual core 65nm
Intel Octa core 22nm
8 cores instead of 1 using the same space
3 times faster
10 times less power consumption

7. SUPPLY VOLTAGE SCALE DOWN
This application note
Supply (V)
5.0
0.9 V inside, 1.5V outside
3.3
I/O supply
2.5
Core supply
1.8
1.2
1.0
0.35µ
0.18µ
130n
90n
65n
45n
32n
20n
14n
10n 7n
Technology node

8. REFERENCE PUBLICATIONS
“High Performance Bulk Planar 20nm CMOS Technology for Low Power Mobile Applications”, Huiling Shang, 2012 Symposium on VLSI Technology
Used as a reference for Microwind’s 20nm implementation

9. Effective gate length (nm) 20 MOS variants 5 2 Ion N (mA/µm) at VDD
PERFORMANCE TARGETS
Only a subset of 20-nm variants has been implemented in Microwind
Parameter
Value
In Microwind
VDD core (V)
0.9
Effective gate length (nm) 20
MOS variants 5 2
Ion N (mA/µm) at VDD
0.9 (LL) 1.1 (HS)
Ion P (mA/µm) at VDD
0.8 (LL) 1.0 (HS)
Ioff N (nA/µm)
1 (LL) 10 (HS)
Ioff P (nA/µm)
Gate dielectric
HfO2
Gate stack
Al/TiN
Equivalent oxide thickness (nm) 1

10. NMOS 20nm PMOS 20nm uLVT 100 100 Microwind’s High speed
Microwind’s Low Leakage 10
Microwind’s Low Leakage
sLVT
sLVT
LVT
Ioff (nA/µm)
Ioff (nA/µm)
1.0
LVT
1.0
RVT
RVT
0.1
0.1
HLVT
HLVT
0.01
0.01
0.5
1.0
1.5
0.5
1.0
1.5
Ion (mA/µm)
Ion (mA/µm)

11. 6 λ min. metal pitch (here 8 λ)
MOS DEVICE
6 λ min. metal pitch (here 8 λ)
Parameter
20-nm technology
In Microwind
Lambda
11 nm
Minimum gate length
20 nm
2 λ (22 nm)
Minimum gate width
60 nm
6 λ (66 nm)
Metal pitch 64
6 λ minimum width
(here 10 λ)
3 λ min for metal 1
(here 4 λ)
2 λ minimum gate length

12. 20-nm N-channel MOS without strain 20-nm P-channel MOS with strain
MOS 2D CROSS-SECTION Al
Work-function metal based on TiN
Hf02-based high-k oxide above atomic-scale SiO2
Aluminum fill
P-doped substrate
N+ diffusion Al
Work-function metal based on TiN
Hf02-based high-k oxide above atomic-scale SiO2
Aluminum fill
N-doped well
P+ diffusion
(eSiGe)
20-nm N-channel MOS without strain
20-nm P-channel MOS with strain

13. 20-NM PROCESS VIEW
P-channel MOS
N-channel MOS

14. Microwind’s Low Leakage NMOS (RVT) Microwind’s High speed NMOS (SLVT)
MOS VARIANTS
Ion=1.1mA
Ion=0.9mA
Microwind’s Low Leakage NMOS (RVT)
Microwind’s High speed NMOS (SLVT)

15. The option layer enables to changes the MOS option
Low-leakage nMOS
High-Speed nMOS

16. Microwind’s Low Leakage NMOS (RVT) Microwind’s High speed NMOS (SLVT)
ION/IOFF TRADE-OFF
Id/Vg for Vb=0, Vds=0.9 V
Id/Vg for Vb=0, Vds=0.9 V
Ion=1.1mA
Ion=0.9mA
Vt=0.30 V
Vt=0.35V
Ioff=10 nA
Ioff=1 nA
Microwind’s Low Leakage NMOS (RVT)
Microwind’s High speed NMOS (SLVT)

17. Microwind’s Low Leakage NMOS (RVT) Microwind’s High speed NMOS (SLVT)
ION BENEFITS
Ion=1.0mA
Ion=0.8mA
Microwind’s Low Leakage NMOS (RVT)
Microwind’s High speed NMOS (SLVT)

18. Microwind’s Low Leakage PMOS (RVT) Microwind’s High speed PMOS (SLVT)
PMOS TRADE-OFF
Id/Vg for Vb=0, Vds=0.9 V
Id/Vg for Vb=0, Vds=0.9 V
Ion=1.0mA
Ion=0.8mA
Vt=0.30 V
Vt=0.35V
Ioff=10 nA
Ioff=1 nA
Microwind’s Low Leakage PMOS (RVT)
Microwind’s High speed PMOS (SLVT)

19. Dummy gates for increased manufacturability
DUMMY POLY
Dummy gates for increased manufacturability

20. DUMMY POLY
Severe distortion
Reduced distortion

21. Middle-of-the-Line (MOL) 64 50 Not supported Intra-cell routing M1-M3
METAL LAYERS
Only 8 metal layers available in Microwind
Re-assignement of original 11 layers, as close as possible to the original pitch
Parameter
Pitch (nm)
Thickness (nm)
Pitch in Microwind
Purpose
Middle-of-the-Line (MOL) 64 50
Not supported
Intra-cell routing
M1-M3 68
M1-M2: 6 λ (66 nm)
Short routing
M4-M7 80
M3-M4: 8 λ (88 nm)
Medium routing
M8-M9
358
150
M5-M6: 32 λ
Block supply and long routing
M10-M11
1000
200
M7-M8: 92 λ
System supply and IO routing

22. METAL LAYERS

23. For pitch lower than 80nm (M2-M8): simple patterning
DOUBLE PATTERNING
For pitch lower than 80nm (M2-M8): simple patterning
For pitch lower than 80nm (M1-M2): double patterning

24. After fabrication in single patterning
DOUBLE PATTERNING
Initial M1 layer
6 λ minimum pitch
Bridge
After fabrication in single patterning
Open

25. 66 nm pitch M1 patterns need double patterning
Second patterning
First patterning

26. Publication Design in Microwind
RING OSCILLATOR STUDY
Publication
Design in Microwind
A. Scholze “Exploring MOL Design Options for a 20nm CMOS Technology using TCAD”, SISPAD 2011

27. RING OSCILLATOR STUDY

28. RING OSCILLATOR STUDY
With a fanout of 3, around 5ps/stage
Only small gain as compared to 32/28-nm node

29. PROCESS, TEMPERATURE, SUPPLY VARIATIONS
Worst case conditions
Best case conditions

30. 5-stage Ring Oscillator Frequency (FO3) – in GHz
PROCESS, TEMPERATURE, SUPPLY VARIATIONS 70 60
HS-sLVT 50
5-stage Ring Oscillator Frequency (FO3) – in GHz
300% difference 40
LL-RVT 30 20 10
Best case conditions
Fast, low T°, high supply
Worst case conditions: slow, high T°, low supply
Min
Typ
Max
PVT

31. 6-TRANSISTOR MEMORY
0.08 µm2
Shared supply
Shared contacts

32. OR3 GATE

33. OR3 GATE SIMULATION
Manual simulation of the OR3
Any input at 1 (here A) is enough to turn the output to 1

34. CONCLUSION
Major foundries have cooperated to release a common 20-nm technology in 2012
Microwind’s 20-nm rule file has been tuned to this joint technology
VDD passes below the 1V barrier
2 MOS device options implemented: high speed & low leakage
Aggressive 64nm lower metal pitch require double patterning
Dummy poly added for improved manufacturability
Inverter delay with Fanout 3 around 5ps
Up to 300% performance variations in extreme PVT conditions
Future nodes will require FinFET device